[v4] target/loongarch: Small enhancement about TLB flush

[PATCH v4 05/13] target/loongarch: Fix page size set issue with CSR_STLBPS

Posted by Bibo Mao 5 months, 1 week ago

When modify register CSR_STLBPS, the page size should come from
input parameter rather than old value.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu-csr.h        | 1 +
 target/loongarch/tcg/csr_helper.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f30..1a311bf06a 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -106,6 +106,7 @@ FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
 
 #define LOONGARCH_CSR_STLBPS         0x1e /* Stlb page size */
 FIELD(CSR_STLBPS, PS, 0, 5)
+FIELD(CSR_STLBPS, RESERVE, 5, 27)
 
 #define LOONGARCH_CSR_RVACFG         0x1f /* Reduced virtual address config */
 FIELD(CSR_RVACFG, RBITS, 0, 4)
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 0d99e2c92b..eb60fefa82 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -26,13 +26,14 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
      * The real hardware only supports the min tlb_ps is 12
      * tlb_ps=0 may cause undefined-behavior.
      */
-    uint8_t tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+    uint8_t tlb_ps = FIELD_EX64(val, CSR_STLBPS, PS);
     if (!check_ps(env, tlb_ps)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "Attempted set ps %d\n", tlb_ps);
     } else {
         /* Only update PS field, reserved bit keeps zero */
-        env->CSR_STLBPS = FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps);
+        val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
+        env->CSR_STLBPS = val;
     }
 
     return old_v;
-- 
2.39.3

Re: [PATCH v4 05/13] target/loongarch: Fix page size set issue with CSR_STLBPS

Posted by gaosong 4 months, 2 weeks ago

在 2025/9/6 下午3:04, Bibo Mao 写道:
> When modify register CSR_STLBPS, the page size should come from
> input parameter rather than old value.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>   target/loongarch/cpu-csr.h        | 1 +
>   target/loongarch/tcg/csr_helper.c | 5 +++--
>   2 files changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index 0834e91f30..1a311bf06a 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -106,6 +106,7 @@ FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
>   
>   #define LOONGARCH_CSR_STLBPS         0x1e /* Stlb page size */
>   FIELD(CSR_STLBPS, PS, 0, 5)
> +FIELD(CSR_STLBPS, RESERVE, 5, 27)
>   
>   #define LOONGARCH_CSR_RVACFG         0x1f /* Reduced virtual address config */
>   FIELD(CSR_RVACFG, RBITS, 0, 4)
> diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
> index 0d99e2c92b..eb60fefa82 100644
> --- a/target/loongarch/tcg/csr_helper.c
> +++ b/target/loongarch/tcg/csr_helper.c
> @@ -26,13 +26,14 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
>        * The real hardware only supports the min tlb_ps is 12
>        * tlb_ps=0 may cause undefined-behavior.
>        */
> -    uint8_t tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> +    uint8_t tlb_ps = FIELD_EX64(val, CSR_STLBPS, PS);
>       if (!check_ps(env, tlb_ps)) {
>           qemu_log_mask(LOG_GUEST_ERROR,
>                         "Attempted set ps %d\n", tlb_ps);
>       } else {
>           /* Only update PS field, reserved bit keeps zero */
> -        env->CSR_STLBPS = FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps);
> +        val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
> +        env->CSR_STLBPS = val;
>       }
>   
>       return old_v;