1. Patchew
  2. QEMU
  3. [PATCH v6 00/11] hw/loongarch: add the advanced extended interrupt controllers (AVECINTC) support
  4. View patch

[PATCH v6 04/11] loongarch: add a advance interrupt controller device

Song Gao posted 11 patches 5 months, 1 week ago
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>, Jiaxun Yang <jiaxun.yang@flygoat.com>
There is a newer version of this series
[PATCH v6 04/11] loongarch: add a advance interrupt controller device
Posted by Song Gao 5 months, 1 week ago 
Add Loongarch  advance interrupt controller device base Definition.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/Kconfig                  |  3 ++
 hw/intc/loongarch_avec.c         | 68 ++++++++++++++++++++++++++++++++
 hw/intc/meson.build              |  1 +
 hw/loongarch/Kconfig             |  1 +
 include/hw/intc/loongarch_avec.h | 35 ++++++++++++++++
 5 files changed, 108 insertions(+)
 create mode 100644 hw/intc/loongarch_avec.c
 create mode 100644 include/hw/intc/loongarch_avec.h

diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 7547528f2c..b9266dc269 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -109,3 +109,6 @@ config LOONGARCH_PCH_MSI
 
 config LOONGARCH_EXTIOI
     bool
+
+config LOONGARCH_AVEC
+    bool
diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
new file mode 100644
index 0000000000..5a3e7ecc03
--- /dev/null
+++ b/hw/intc/loongarch_avec.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU Loongson  Advance interrupt controller.
+ *
+ * Copyright (C) 2025 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/intc/loongarch_pch_msi.h"
+#include "hw/intc/loongarch_pch_pic.h"
+#include "hw/intc/loongarch_avec.h"
+#include "hw/pci/msi.h"
+#include "hw/misc/unimp.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+#include "hw/qdev-properties.h"
+
+
+static void loongarch_avec_realize(DeviceState *dev, Error **errp)
+{
+    LoongArchAVECClass *lac = LOONGARCH_AVEC_GET_CLASS(dev);
+
+    Error *local_err = NULL;
+    lac->parent_realize(dev, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    return;
+}
+
+static void loongarch_avec_unrealize(DeviceState *dev)
+{
+    return;
+}
+
+static void loongarch_avec_init(Object *obj)
+{
+    return;
+}
+
+static void loongarch_avec_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    LoongArchAVECClass *lac = LOONGARCH_AVEC_CLASS(klass);
+
+    dc->unrealize = loongarch_avec_unrealize;
+    device_class_set_parent_realize(dc, loongarch_avec_realize,
+                                    &lac->parent_realize);
+}
+
+static const TypeInfo loongarch_avec_info = {
+    .name          = TYPE_LOONGARCH_AVEC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(LoongArchAVECState),
+    .instance_init = loongarch_avec_init,
+    .class_init    = loongarch_avec_class_init,
+};
+
+static void loongarch_avec_register_types(void)
+{
+    type_register_static(&loongarch_avec_info);
+}
+
+type_init(loongarch_avec_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 3137521a4a..cf2c47cd53 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -80,3 +80,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_
 specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c', 'loongarch_extioi_common.c'))
 specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'],
                if_true: files('loongarch_extioi_kvm.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_AVEC', if_true: files('loongarch_avec.c'))
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index bb2838b7b5..1bf240b1e2 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -15,6 +15,7 @@ config LOONGARCH_VIRT
     select LOONGARCH_PCH_PIC
     select LOONGARCH_PCH_MSI
     select LOONGARCH_EXTIOI
+    select LOONGARCH_AVEC
     select LS7A_RTC
     select SMBIOS
     select ACPI_CPU_HOTPLUG
diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_avec.h
new file mode 100644
index 0000000000..92e2ca9590
--- /dev/null
+++ b/include/hw/intc/loongarch_avec.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch  Advance interrupt controller definitions
+ *
+ * Copyright (C) 2025 Loongson Technology Corporation Limited
+ */
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/loongarch/virt.h"
+
+
+#define NR_VECTORS     256
+
+#define TYPE_LOONGARCH_AVEC "loongarch_avec"
+OBJECT_DECLARE_TYPE(LoongArchAVECState, LoongArchAVECClass, LOONGARCH_AVEC)
+
+typedef struct AVECCore {
+    CPUState *cpu;
+    qemu_irq parent_irq;
+    uint64_t arch_id;
+} AVECCore;
+
+struct LoongArchAVECState {
+    SysBusDevice parent_obj;
+    AVECCore *cpu;
+    uint32_t num_cpu;
+};
+
+struct LoongArchAVECClass {
+    SysBusDeviceClass parent_class;
+
+    DeviceRealize parent_realize;
+    DeviceUnrealize parent_unrealize;
+};
-- 
2.41.0
Re: [PATCH v6 04/11] loongarch: add a advance interrupt controller device
Posted by Bibo Mao 5 months, 1 week ago 

On 2025/9/4 下午8:18, Song Gao wrote:
> Add Loongarch  advance interrupt controller device base Definition.
Two space here with "Loongarch  advance", maybe advanced is better.

Otherwise looks good to me.

Reviewed-by: Bibo Mao <maobibo@loongson.cn>

> 
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   hw/intc/Kconfig                  |  3 ++
>   hw/intc/loongarch_avec.c         | 68 ++++++++++++++++++++++++++++++++
>   hw/intc/meson.build              |  1 +
>   hw/loongarch/Kconfig             |  1 +
>   include/hw/intc/loongarch_avec.h | 35 ++++++++++++++++
>   5 files changed, 108 insertions(+)
>   create mode 100644 hw/intc/loongarch_avec.c
>   create mode 100644 include/hw/intc/loongarch_avec.h
> 
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 7547528f2c..b9266dc269 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -109,3 +109,6 @@ config LOONGARCH_PCH_MSI
>   
>   config LOONGARCH_EXTIOI
>       bool
> +
> +config LOONGARCH_AVEC
> +    bool
> diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
> new file mode 100644
> index 0000000000..5a3e7ecc03
> --- /dev/null
> +++ b/hw/intc/loongarch_avec.c
> @@ -0,0 +1,68 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU Loongson  Advance interrupt controller.
> + *
> + * Copyright (C) 2025 Loongson Technology Corporation Limited
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/irq.h"
> +#include "hw/intc/loongarch_pch_msi.h"
> +#include "hw/intc/loongarch_pch_pic.h"
> +#include "hw/intc/loongarch_avec.h"
> +#include "hw/pci/msi.h"
> +#include "hw/misc/unimp.h"
> +#include "migration/vmstate.h"
> +#include "trace.h"
> +#include "hw/qdev-properties.h"
> +
> +
> +static void loongarch_avec_realize(DeviceState *dev, Error **errp)
> +{
> +    LoongArchAVECClass *lac = LOONGARCH_AVEC_GET_CLASS(dev);
> +
> +    Error *local_err = NULL;
> +    lac->parent_realize(dev, &local_err);
> +    if (local_err) {
> +        error_propagate(errp, local_err);
> +        return;
> +    }
> +
> +    return;
> +}
> +
> +static void loongarch_avec_unrealize(DeviceState *dev)
> +{
> +    return;
> +}
> +
> +static void loongarch_avec_init(Object *obj)
> +{
> +    return;
> +}
> +
> +static void loongarch_avec_class_init(ObjectClass *klass, const void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    LoongArchAVECClass *lac = LOONGARCH_AVEC_CLASS(klass);
> +
> +    dc->unrealize = loongarch_avec_unrealize;
> +    device_class_set_parent_realize(dc, loongarch_avec_realize,
> +                                    &lac->parent_realize);
> +}
> +
> +static const TypeInfo loongarch_avec_info = {
> +    .name          = TYPE_LOONGARCH_AVEC,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(LoongArchAVECState),
> +    .instance_init = loongarch_avec_init,
> +    .class_init    = loongarch_avec_class_init,
> +};
> +
> +static void loongarch_avec_register_types(void)
> +{
> +    type_register_static(&loongarch_avec_info);
> +}
> +
> +type_init(loongarch_avec_register_types)
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 3137521a4a..cf2c47cd53 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -80,3 +80,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_
>   specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c', 'loongarch_extioi_common.c'))
>   specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'],
>                  if_true: files('loongarch_extioi_kvm.c'))
> +specific_ss.add(when: 'CONFIG_LOONGARCH_AVEC', if_true: files('loongarch_avec.c'))
> diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
> index bb2838b7b5..1bf240b1e2 100644
> --- a/hw/loongarch/Kconfig
> +++ b/hw/loongarch/Kconfig
> @@ -15,6 +15,7 @@ config LOONGARCH_VIRT
>       select LOONGARCH_PCH_PIC
>       select LOONGARCH_PCH_MSI
>       select LOONGARCH_EXTIOI
> +    select LOONGARCH_AVEC
>       select LS7A_RTC
>       select SMBIOS
>       select ACPI_CPU_HOTPLUG
> diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_avec.h
> new file mode 100644
> index 0000000000..92e2ca9590
> --- /dev/null
> +++ b/include/hw/intc/loongarch_avec.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch  Advance interrupt controller definitions
> + *
> + * Copyright (C) 2025 Loongson Technology Corporation Limited
> + */
> +
> +#include "qom/object.h"
> +#include "hw/sysbus.h"
> +#include "hw/loongarch/virt.h"
> +
> +
> +#define NR_VECTORS     256
> +
> +#define TYPE_LOONGARCH_AVEC "loongarch_avec"
> +OBJECT_DECLARE_TYPE(LoongArchAVECState, LoongArchAVECClass, LOONGARCH_AVEC)
> +
> +typedef struct AVECCore {
> +    CPUState *cpu;
> +    qemu_irq parent_irq;
> +    uint64_t arch_id;
> +} AVECCore;
> +
> +struct LoongArchAVECState {
> +    SysBusDevice parent_obj;
> +    AVECCore *cpu;
> +    uint32_t num_cpu;
> +};
> +
> +struct LoongArchAVECClass {
> +    SysBusDeviceClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    DeviceUnrealize parent_unrealize;
> +};
>

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.