[v2] Add Zvqdotq support

[RFC PATCH v2 0/3] Add Zvqdotq support

Max Chou posted 3 patches 2 days, 23 hours ago

Diff against v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250903130125.1701363-1-max.chou@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c                            |  2 +
target/riscv/cpu_cfg_fields.h.inc             |  1 +
target/riscv/helper.h                         | 10 +++
target/riscv/insn32.decode                    |  9 +++
target/riscv/insn_trans/trans_rvzvqdotq.c.inc | 61 +++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                    |  5 ++
target/riscv/translate.c                      |  1 +
target/riscv/vector_helper.c                  | 61 +++++++++++++++++++
8 files changed, 150 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzvqdotq.c.inc

Expand all Fold all

[RFC PATCH v2 0/3] Add Zvqdotq support

Posted by Max Chou 2 days, 23 hours ago

This patch series adds Zvqdotq support.

The isa spec of Zvqdotq extension is not ratified yet, so this patch series
is based on the latest draft of the spec (v0.0.2) and make the Zvqdotq
extension as an experimental extension.

The draft of the Zvqdotq isa spec:
https://github.com/riscv/riscv-dot-product

v2:
* Remove unnecessary variable and mask (Thanks for Richard Henderson's
  suggestion)

Max Chou (3):
  target/riscv: Add Zvqdotq cfg property
  target/riscv: rvv: Add Zvqdotq support
  target/riscv: Expose Zvqdotq extension as a cpu property

 target/riscv/cpu.c                            |  2 +
 target/riscv/cpu_cfg_fields.h.inc             |  1 +
 target/riscv/helper.h                         | 10 +++
 target/riscv/insn32.decode                    |  9 +++
 target/riscv/insn_trans/trans_rvzvqdotq.c.inc | 61 +++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                    |  5 ++
 target/riscv/translate.c                      |  1 +
 target/riscv/vector_helper.c                  | 61 +++++++++++++++++++
 8 files changed, 150 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rvzvqdotq.c.inc

--
2.39.3