On 3/9/25 12:06, Philippe Mathieu-Daudé wrote:
> From: Mohamed Mediouni <mohamed@unpredictable.fr>
>
> Creating a vCPU locks out APIs such as hv_gic_create().
>
> As a result, switch to using the hv_vcpu_config_get_feature_reg interface.
>
> Besides, all the following methods must be run on a vCPU thread:
>
> - hv_vcpu_create()
> - hv_vcpu_get_sys_reg()
> - hv_vcpu_destroy()
>
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Message-ID: <20250808070137.48716-3-mohamed@unpredictable.fr>
> [PMD: Release config calling os_release()]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/arm/hvf/hvf.c | 36 +++++++++++++++---------------------
> 1 file changed, 15 insertions(+), 21 deletions(-)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 3039c0987dc..fd209d23c1e 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -869,24 +869,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> {
> ARMISARegisters host_isar = {};
> const struct isar_regs {
> - int reg;
> + hv_feature_reg_t reg;
> uint64_t *val;
> } regs[] = {
> - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
> /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
> - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] },
> + { HV_FEATURE_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] },
> /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
> + { HV_FEATURE_REG_CTR_EL0, &host_isar.idregs[CTR_EL0_IDX] },
> + { HV_FEATURE_REG_CLIDR_EL1, &host_isar.idregs[CLIDR_EL1_IDX] },
I'd rather add the 2 last ones in a distinct patch, keeping
this one as a simple API conversion.
> };
> - hv_vcpu_t fd;
> hv_return_t r = HV_SUCCESS;
> - hv_vcpu_exit_t *exit;
> + hv_vcpu_config_t config = hv_vcpu_config_create();
> uint64_t t;
> int i;
>
> @@ -897,17 +898,10 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> (1ULL << ARM_FEATURE_PMU) |
> (1ULL << ARM_FEATURE_GENERIC_TIMER);
>
> - /* We set up a small vcpu to extract host registers */
> -
> - if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
> - return false;
> - }
> -
> for (i = 0; i < ARRAY_SIZE(regs); i++) {
> - r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);
> + r |= hv_vcpu_config_get_feature_reg(config, regs[i].reg, regs[i].val);
> }
> - r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
> - r |= hv_vcpu_destroy(fd);
> + os_release(config);
>
> /*
> * Hardcode MIDR because Apple deliberately doesn't expose a divergent