> On 3 Sep 2025, at 12.06, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> From: Mohamed Mediouni <mohamed@unpredictable.fr>
>
> Hardcode MIDR because Apple deliberately doesn't expose
> a divergent MIDR across systems.
>
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/arm/hvf/hvf.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 5b3c34014a5..3039c0987dc 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -887,6 +887,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> hv_vcpu_t fd;
> hv_return_t r = HV_SUCCESS;
> hv_vcpu_exit_t *exit;
> + uint64_t t;
> int i;
>
> ahcf->dtb_compatible = "arm,armv8";
> @@ -908,6 +909,17 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
This line above seems redundant, if we override it in the following.
> r |= hv_vcpu_destroy(fd);
>
> + /*
> + * Hardcode MIDR because Apple deliberately doesn't expose a divergent
> + * MIDR across systems.
> + */
> + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0x61); /* Apple */
> + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); /* v7 or later */
> + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 0);
> + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
> + t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
> + ahcf->midr = t;
> +
> clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
>
> /*
> --
> 2.51.0
>