[PATCH v2 17/40] target/hexagon: Define DCache states

Brian Cain posted 40 patches 3 weeks, 5 days ago
Maintainers: Brian Cain <brian.cain@oss.qualcomm.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Laurent Vivier <laurent@vivier.eu>, Alessandro Di Federico <ale@rev.ng>, Anton Johansson <anjo@rev.ng>
[PATCH v2 17/40] target/hexagon: Define DCache states
Posted by Brian Cain 3 weeks, 5 days ago
From: Brian Cain <bcain@quicinc.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu_bits.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index b118761e05..c7cc426ec8 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -101,6 +101,13 @@ enum hex_cause {
     HEX_CAUSE_VIC3 = 0x0c5,
 };
 
+enum data_cache_state {
+    HEX_DC_STATE_INVALID   = 0x0,
+    HEX_DC_STATE_VALID     = 0x1,
+    HEX_DC_STATE_RESERVED  = 0x2,
+    HEX_DC_STATE_UNUSED_WT = 0x3,
+};
+
 #define PACKET_WORDS_MAX         4
 
 static inline uint32_t parse_bits(uint32_t encoding)
-- 
2.34.1