[PATCH v2 10/40] target/hexagon: Add memory order definition

From: Brian Cain <bcain@quicinc.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu-param.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 635d509e74..22bffa7881 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -25,4 +25,9 @@
 
 #define TARGET_INSN_START_EXTRA_WORDS 0
 
+/*
+ * Hexagon processors have a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL)
+
 #endif
-- 
2.34.1

• [PATCH v2 01/40] docs: Add hexagon sysemu docs
• [PATCH v2 02/40] docs/system: Add hexagon CPU emulation
• [PATCH v2 03/40] target/hexagon: Fix badva reference, delete CAUSE
• [PATCH v2 04/40] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
• [PATCH v2 05/40] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py
• [PATCH v2 06/40] target/hexagon: Make gen_exception_end_tb non-static
• [PATCH v2 07/40] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags()
• [PATCH v2 08/40] target/hexagon: Add system event, cause codes
• [PATCH v2 09/40] target/hexagon: Add privilege check, use tag_ignore()
• [PATCH v2 10/40] target/hexagon: Add memory order definition
• [PATCH v2 11/40] target/hexagon: Add a placeholder fp exception
• [PATCH v2 12/40] target/hexagon: Add guest, system reg number defs
• [PATCH v2 13/40] target/hexagon: Add guest, system reg number state
• [PATCH v2 14/40] target/hexagon: Add TCG values for sreg, greg
• [PATCH v2 15/40] target/hexagon: Add guest/sys reg writes to DisasContext
• [PATCH v2 16/40] target/hexagon: Add imported macro, attr defs for sysemu
• [PATCH v2 17/40] target/hexagon: Define DCache states
• [PATCH v2 18/40] target/hexagon: Add new macro definitions for sysemu
• [PATCH v2 19/40] target/hexagon: Add handlers for guest/sysreg r/w
• [PATCH v2 20/40] target/hexagon: Add placeholder greg/sreg r/w helpers
• [PATCH v2 21/40] target/hexagon: Add vmstate representation
• [PATCH v2 22/40] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()
• [PATCH v2 23/40] target/hexagon: Define register fields for system regs
• [PATCH v2 24/40] target/hexagon: Implement do_raise_exception()
• [PATCH v2 25/40] target/hexagon: Add system reg insns
• [PATCH v2 26/40] target/hexagon: Add sysemu TCG overrides
• [PATCH v2 27/40] target/hexagon: Add implicit attributes to sysemu macros
• [PATCH v2 28/40] target/hexagon: Add TCG overrides for int handler insts
• [PATCH v2 29/40] target/hexagon: Add TCG overrides for thread ctl
• [PATCH v2 30/40] target/hexagon: Add TCG overrides for rte, nmi
• [PATCH v2 31/40] target/hexagon: Add sreg_{read,write} helpers
• [PATCH v2 32/40] target/hexagon: Add locks, id, next_PC to state
• [PATCH v2 33/40] target/hexagon: Add a TLB count property
• [PATCH v2 34/40] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc
• [PATCH v2 35/40] target/hexagon: Add stubs for modify_ssr/get_exe_mode
• [PATCH v2 36/40] target/hexagon: Add gdb support for sys regs
• [PATCH v2 37/40] target/hexagon: Add initial MMU model
• [PATCH v2 38/40] target/hexagon: Add clear_wait_mode() definition
• [PATCH v2 39/40] target/hexagon: Define f{S,G}ET_FIELD macros
• [PATCH v2 40/40] target/hexagon: Add hex_interrupts support