tcg/i386: Improve vector shifts

[PATCH v2 0/5] tcg/i386: Improve vector shifts

Richard Henderson posted 5 patches 4 weeks, 1 day ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250830033926.372955-1-richard.henderson@linaro.org

Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>

host/include/i386/host/cpuinfo.h |  1 +
include/qemu/cpuid.h             |  3 ++
util/cpuinfo-i386.c              |  1 +
tcg/i386/tcg-target-opc.h.inc    |  1 +
tcg/i386/tcg-target.c.inc        | 91 +++++++++++++++++++++++++++++---
5 files changed, 91 insertions(+), 6 deletions(-)

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[PATCH v2 0/5] tcg/i386: Improve vector shifts

Posted by Richard Henderson 4 weeks, 1 day ago

x86 doesn't directly support 8-bit vector shifts, so we have
some 2 to 5 insn expansions.  With VGF2P8AFFINEQB, we can do
it in 1 insn, plus a (possibly shared) constant load.

Changes for v2:
  - Use PCMPGT for arithmetic right-shift of bits-1 (paolo).
  - Tidy an instance of non-canonical operand ordering.

r~

Richard Henderson (5):
  cpuinfo/i386: Detect GFNI as an AVX extension
  tcg/i386: Expand sari of bits-1 as pcmpgt
  tcg/i386: Use canonical operand ordering in expand_vec_sari
  tcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vec
  tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts

 host/include/i386/host/cpuinfo.h |  1 +
 include/qemu/cpuid.h             |  3 ++
 util/cpuinfo-i386.c              |  1 +
 tcg/i386/tcg-target-opc.h.inc    |  1 +
 tcg/i386/tcg-target.c.inc        | 91 +++++++++++++++++++++++++++++---
 5 files changed, 91 insertions(+), 6 deletions(-)

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2.43.0