Hi Alireza,
On 8/27/25 11:21, Alireza Sanaee wrote:
> This patch addresses cache description in the `aarch64_max_tcg_initfn`
> function for cpu=max. It introduces three layers of caches and modifies
> the cache description registers accordingly.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> ---
> target/arm/tcg/cpu64.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 35cddbafa4..bf1372ecdf 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -1093,6 +1093,19 @@ void aarch64_max_tcg_initfn(Object *obj)
> uint64_t t;
> uint32_t u;
>
> + /*
> + * Expanded cache set
> + */
Can't make sense of this comment. I think it can be confused with anything
related to "Expanded cache index" (FEAT_CCIDX), which is a format not being
used to set the caches below, so maybe remove it?
> + SET_IDREG(isar, CLIDR, 0x8200123); /* 4 4 3 in 3 bit fields */
Please improve the comment on CLIDR fields here if you want to keep it, like you
did below, i.e., stating what is selected for LoUU, LoC, LoUIS, and the type
of caches at L1, L2, and L3, like "Separate", "Unified", "Unified" etc.
Just to confirm, the ICB field is set to "Not disclosed by this mechanism" because
we don't want to bother setting it as we customize/tweak the topology?
> + /* 64KB L1 dcache */
> + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
> + /* 64KB L1 icache */
> + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
> + /* 1MB L2 unified cache */
> + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
> + /* 2MB L3 unified cache */
> + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7);
> +
> /*
> * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
> * to because we started with aarch64_a57_initfn(). A 'max' CPU might
Cheers,
Gustavo