[PATCH 06/10] hw/pci-host/designware: Fix I/O range

Bernhard Beschow posted 10 patches 2 months, 3 weeks ago
Maintainers: Bernhard Beschow <shentey@gmail.com>, Peter Maydell <peter.maydell@linaro.org>, Andrey Smirnov <andrew.smirnov@gmail.com>
[PATCH 06/10] hw/pci-host/designware: Fix I/O range
Posted by Bernhard Beschow 2 months, 3 weeks ago
Fix the size of the I/O space to be 64KiB, as defined by the PCI
specification. This fixes illegal memory access by guests in the
imx8mp-evk machine such that the FSL_IMX8MP_PCIE1_MEM unimplemented
region can be omitted there.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/pci-host/designware.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 7342207eb3..1e29b7e6be 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -684,7 +684,7 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
                           "pcie.reg", 4 * 1024);
     sysbus_init_mmio(sbd, &s->mmio);
 
-    memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
+    memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", UINT16_MAX);
     memory_region_init(&s->pci.memory, OBJECT(s),
                        "pcie-bus-memory",
                        UINT64_MAX);
-- 
2.50.1
Re: [PATCH 06/10] hw/pci-host/designware: Fix I/O range
Posted by Peter Maydell 2 months, 1 week ago
On Wed, 20 Aug 2025 at 22:19, Bernhard Beschow <shentey@gmail.com> wrote:
>
> Fix the size of the I/O space to be 64KiB, as defined by the PCI
> specification. This fixes illegal memory access by guests in the
> imx8mp-evk machine such that the FSL_IMX8MP_PCIE1_MEM unimplemented
> region can be omitted there.
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> ---
>  hw/pci-host/designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 7342207eb3..1e29b7e6be 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -684,7 +684,7 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
>                            "pcie.reg", 4 * 1024);
>      sysbus_init_mmio(sbd, &s->mmio);
>
> -    memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
> +    memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", UINT16_MAX);

This isn't 64K, it's 1 byte less than 64K. You want
64 * KiB   or something similar.

(The memory APIs have a special case for "size 2^64" where
you can pass it UINT64_MAX, but any sizes below that you
pass in the actual size: the special case is just so we
can use a uint64_t type for the argument without losing
the ability to specify a size that covers the full 64-bit
address space.)

>      memory_region_init(&s->pci.memory, OBJECT(s),
>                         "pcie-bus-memory",
>                         UINT64_MAX);

(We seem to have a similar bug in xilinx-pcie.c.)

-- PMM