[PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs

Kane Chen via posted 10 patches 3 months ago
Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>
[PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
Posted by Kane Chen via 3 months ago
From: Kane-Chen-AS <kane_chen@aspeedtech.com>

The has_otp attribute is enabled in the SBC subclasses for AST1030 to
control the presence of OTP support per SoC type.

Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
 include/hw/misc/aspeed_sbc.h |  1 +
 hw/arm/aspeed_ast10x0.c      |  2 +-
 hw/misc/aspeed_sbc.c         | 16 ++++++++++++++++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
index 0c2746d392..7d640a022e 100644
--- a/include/hw/misc/aspeed_sbc.h
+++ b/include/hw/misc/aspeed_sbc.h
@@ -14,6 +14,7 @@
 
 #define TYPE_ASPEED_SBC "aspeed.sbc"
 #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
+#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0"
 OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
 
 #define ASPEED_SBC_NR_REGS (0x93c >> 2)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index e6e1ee63c1..c446e70b24 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
 
     object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
 
-    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
+    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC);
 
     for (i = 0; i < sc->wdts_num; i++) {
         snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
index b56a8b7678..052c70fd42 100644
--- a/hw/misc/aspeed_sbc.c
+++ b/hw/misc/aspeed_sbc.c
@@ -285,9 +285,25 @@ static const TypeInfo aspeed_ast2600_sbc_info = {
     .class_init = aspeed_ast2600_sbc_class_init,
 };
 
+static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
+
+    dc->desc = "AST10X0 Secure Boot Controller";
+    sc->has_otp = true;
+}
+
+static const TypeInfo aspeed_ast10x0_sbc_info = {
+    .name = TYPE_ASPEED_AST10X0_SBC,
+    .parent = TYPE_ASPEED_SBC,
+    .class_init = aspeed_ast10x0_sbc_class_init,
+};
+
 static void aspeed_sbc_register_types(void)
 {
     type_register_static(&aspeed_ast2600_sbc_info);
+    type_register_static(&aspeed_ast10x0_sbc_info);
     type_register_static(&aspeed_sbc_info);
 }
 
-- 
2.43.0
Re: [SPAM] [PATCH v5 06/10] hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
Posted by Cédric Le Goater 2 months, 2 weeks ago
On 8/12/25 11:40, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> 
> The has_otp attribute is enabled in the SBC subclasses for AST1030 to
> control the presence of OTP support per SoC type.
> 
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>



Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   include/hw/misc/aspeed_sbc.h |  1 +
>   hw/arm/aspeed_ast10x0.c      |  2 +-
>   hw/misc/aspeed_sbc.c         | 16 ++++++++++++++++
>   3 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h
> index 0c2746d392..7d640a022e 100644
> --- a/include/hw/misc/aspeed_sbc.h
> +++ b/include/hw/misc/aspeed_sbc.h
> @@ -14,6 +14,7 @@
>   
>   #define TYPE_ASPEED_SBC "aspeed.sbc"
>   #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
> +#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0"
>   OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
>   
>   #define ASPEED_SBC_NR_REGS (0x93c >> 2)
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index e6e1ee63c1..c446e70b24 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj)
>   
>       object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
>   
> -    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
> +    object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC);
>   
>       for (i = 0; i < sc->wdts_num; i++) {
>           snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
> diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c
> index b56a8b7678..052c70fd42 100644
> --- a/hw/misc/aspeed_sbc.c
> +++ b/hw/misc/aspeed_sbc.c
> @@ -285,9 +285,25 @@ static const TypeInfo aspeed_ast2600_sbc_info = {
>       .class_init = aspeed_ast2600_sbc_class_init,
>   };
>   
> +static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    AspeedSBCClass *sc = ASPEED_SBC_CLASS(klass);
> +
> +    dc->desc = "AST10X0 Secure Boot Controller";
> +    sc->has_otp = true;
> +}
> +
> +static const TypeInfo aspeed_ast10x0_sbc_info = {
> +    .name = TYPE_ASPEED_AST10X0_SBC,
> +    .parent = TYPE_ASPEED_SBC,
> +    .class_init = aspeed_ast10x0_sbc_class_init,
> +};
> +
>   static void aspeed_sbc_register_types(void)
>   {
>       type_register_static(&aspeed_ast2600_sbc_info);
> +    type_register_static(&aspeed_ast10x0_sbc_info);
>       type_register_static(&aspeed_sbc_info);
>   }
>