Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
hw/arm/virt.c | 3 +
hw/intc/arm_gicv3_common.c | 3 +
hw/intc/arm_gicv3_whpx.c | 261 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
include/hw/intc/arm_gicv3_common.h | 3 +
5 files changed, 271 insertions(+)
create mode 100644 hw/intc/arm_gicv3_whpx.c
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 5951b331f3..98a1c74c42 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -49,6 +49,7 @@
#include "system/tcg.h"
#include "system/kvm.h"
#include "system/hvf.h"
+#include "system/whpx.h"
#include "system/qtest.h"
#include "hw/loader.h"
#include "qapi/error.h"
@@ -2060,6 +2061,8 @@ static void finalize_gic_version(VirtMachineState *vms)
/* KVM w/o kernel irqchip can only deal with GICv2 */
gics_supported |= VIRT_GIC_VERSION_2_MASK;
accel_name = "KVM with kernel-irqchip=off";
+ } else if (whpx_enabled()) {
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
} else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
gics_supported |= VIRT_GIC_VERSION_2_MASK;
if (module_object_class_by_name("arm-gicv3")) {
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index e438d8c042..8b85b60c9b 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -32,6 +32,7 @@
#include "gicv3_internal.h"
#include "hw/arm/linux-boot-if.h"
#include "system/kvm.h"
+#include "system/whpx.h"
static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
@@ -662,6 +663,8 @@ const char *gicv3_class_name(void)
{
if (kvm_irqchip_in_kernel()) {
return "kvm-arm-gicv3";
+ } else if (whpx_enabled()) {
+ return TYPE_WHPX_GICV3;
} else {
if (kvm_enabled()) {
error_report("Userspace GICv3 is not supported with KVM");
diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c
new file mode 100644
index 0000000000..ead4e167c5
--- /dev/null
+++ b/hw/intc/arm_gicv3_whpx.c
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * ARM Generic Interrupt Controller using HVF platform support
+ *
+ * Copyright (c) 2025 Mohamed Mediouni
+ * Based on vGICv3 KVM code by Pavel Fedin
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/intc/arm_gicv3_common.h"
+#include "qemu/error-report.h"
+#include "qemu/module.h"
+#include "system/runstate.h"
+#include "system/whpx.h"
+#include "system/whpx-internal.h"
+#include "gicv3_internal.h"
+#include "vgic_common.h"
+#include "qom/object.h"
+#include "target/arm/cpregs.h"
+
+#include "hw/arm/bsa.h"
+#include <winhvplatform.h>
+#include <winhvplatformdefs.h>
+#include <winnt.h>
+
+struct WHPXARMGICv3Class {
+ ARMGICv3CommonClass parent_class;
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+typedef struct WHPXARMGICv3Class WHPXARMGICv3Class;
+
+/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3State, WHPXARMGICv3Class,
+ WHPX_GICV3, TYPE_WHPX_GICV3);
+
+static void whpx_gicv3_check(GICv3State *s)
+{
+}
+
+static void whpx_gicv3_put_cpu(CPUState *cpu_state, run_on_cpu_data arg)
+{
+}
+
+static void whpx_gicv3_put(GICv3State *s)
+{
+ int ncpu;
+
+ whpx_gicv3_check(s);
+
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+ run_on_cpu_data data;
+ data.host_ptr = &s->cpu[ncpu];
+ run_on_cpu(s->cpu[ncpu].cpu, whpx_gicv3_put_cpu, data);
+ }
+}
+
+static void whpx_gicv3_get_cpu(CPUState *cpu_state, run_on_cpu_data arg)
+{
+}
+
+static void whpx_gicv3_get(GICv3State *s)
+{
+ int ncpu;
+
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+ run_on_cpu_data data;
+ data.host_ptr = &s->cpu[ncpu];
+ run_on_cpu(s->cpu[ncpu].cpu, whpx_gicv3_get_cpu, data);
+ }
+}
+
+static void whpx_gicv3_set_irq(void *opaque, int irq, int level)
+{
+ struct whpx_state *whpx = &whpx_global;
+
+ GICv3State *s = (GICv3State *)opaque;
+ if (irq > s->num_irq) {
+ return;
+ }
+ WHV_INTERRUPT_TYPE interrupt_type = WHvArm64InterruptTypeFixed;
+ WHV_INTERRUPT_CONTROL interrupt_control = {
+ interrupt_type = WHvArm64InterruptTypeFixed,
+ .RequestedVector = GIC_INTERNAL + irq, .InterruptControl.Asserted = level};
+
+ whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control,
+ sizeof(interrupt_control));
+}
+
+static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ GICv3State *s;
+ GICv3CPUState *c;
+
+ c = (GICv3CPUState *)env->gicv3state;
+ s = c->gic;
+
+ c->icc_pmr_el1 = 0;
+ /*
+ * Architecturally the reset value of the ICC_BPR registers
+ * is UNKNOWN. We set them all to 0 here; when the kernel
+ * uses these values to program the ICH_VMCR_EL2 fields that
+ * determine the guest-visible ICC_BPR register values, the
+ * hardware's "writing a value less than the minimum sets
+ * the field to the minimum value" behaviour will result in
+ * them effectively resetting to the correct minimum value
+ * for the host GIC.
+ */
+ c->icc_bpr[GICV3_G0] = 0;
+ c->icc_bpr[GICV3_G1] = 0;
+ c->icc_bpr[GICV3_G1NS] = 0;
+
+ c->icc_sre_el1 = 0x7;
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
+
+ if (s->migration_blocker) {
+ return;
+ }
+
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
+}
+
+static void whpx_gicv3_reset_hold(Object *obj, ResetType type)
+{
+ GICv3State *s = ARM_GICV3_COMMON(obj);
+ WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s);
+
+ if (kgc->parent_phases.hold) {
+ kgc->parent_phases.hold(obj, type);
+ }
+
+ whpx_gicv3_put(s);
+}
+
+
+/*
+ * CPU interface registers of GIC needs to be reset on CPU reset.
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
+ * register reset, we define only one register of CPU interface instead
+ * of defining all the registers.
+ */
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
+ /*
+ * If ARM_CP_NOP is used, resetfn is not called,
+ * So ARM_CP_NO_RAW is appropriate type.
+ */
+ .type = ARM_CP_NO_RAW,
+ .access = PL1_RW,
+ .readfn = arm_cp_read_zero,
+ .writefn = arm_cp_write_ignore,
+ /*
+ * We hang the whole cpu interface reset routine off here
+ * rather than parcelling it out into one little function
+ * per register
+ */
+ .resetfn = whpx_gicv3_icc_reset,
+ },
+};
+
+static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE val)
+{
+ struct whpx_state *whpx = &whpx_global;
+ HRESULT hr;
+ hr = whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, cpu->cpu_index,
+ ®, 1, &val);
+
+ if (FAILED(hr)) {
+ error_report("WHPX: Failed to set register %08x, hr=%08lx", reg, hr);
+ }
+}
+
+static void whpx_gicv3_realize(DeviceState *dev, Error **errp)
+{
+ GICv3State *s = WHPX_GICV3(dev);
+ WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s);
+ Error *local_err = NULL;
+ int i;
+
+ kgc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (s->revision != 3) {
+ error_setg(errp, "unsupported GIC revision %d for platform GIC",
+ s->revision);
+ }
+
+ if (s->security_extn) {
+ error_setg(errp, "the platform vGICv3 does not implement the "
+ "security extensions");
+ return;
+ }
+
+ if (s->nmi_support) {
+ error_setg(errp, "NMI is not supported with the platform GIC");
+ return;
+ }
+
+ if (s->nb_redist_regions > 1) {
+ error_setg(errp, "Multiple VGICv3 redistributor regions are not "
+ "supported by WHPX");
+ error_append_hint(errp, "A maximum of %d VCPUs can be used",
+ s->redist_region_count[0]);
+ return;
+ }
+
+ gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL);
+
+ for (i = 0; i < s->num_cpu; i++) {
+ CPUState *cpu_state = qemu_get_cpu(i);
+ ARMCPU *cpu = ARM_CPU(cpu_state);
+ WHV_REGISTER_VALUE val = {.Reg64 = 0x080A0000 + (GICV3_REDIST_SIZE * i)};
+ whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val);
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
+ }
+
+ if (s->maint_irq) {
+ error_setg(errp, "Nested virtualisation not currently supported by WHPX.");
+ return;
+ }
+}
+
+static void whpx_gicv3_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
+ WHPXARMGICv3Class *kgc = WHPX_GICV3_CLASS(klass);
+
+ agcc->pre_save = whpx_gicv3_get;
+ agcc->post_load = whpx_gicv3_put;
+
+ device_class_set_parent_realize(dc, whpx_gicv3_realize,
+ &kgc->parent_realize);
+ resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NULL,
+ &kgc->parent_phases);
+}
+
+static const TypeInfo whpx_arm_gicv3_info = {
+ .name = TYPE_WHPX_GICV3,
+ .parent = TYPE_ARM_GICV3_COMMON,
+ .instance_size = sizeof(GICv3State),
+ .class_init = whpx_gicv3_class_init,
+ .class_size = sizeof(WHPXARMGICv3Class),
+};
+
+static void whpx_gicv3_register_types(void)
+{
+ type_register_static(&whpx_arm_gicv3_info);
+}
+
+type_init(whpx_gicv3_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 3137521a4a..4fc6b78a04 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
+specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('arm_gicv3_whpx.c'))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index c18503869f..7776558a0e 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -306,6 +306,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
+/* Types for GICv3 kernel-irqchip */
+#define TYPE_WHPX_GICV3 "whpx-arm-gicv3"
+
struct ARMGICv3CommonClass {
/*< private >*/
SysBusDeviceClass parent_class;
--
2.39.5 (Apple Git-154)On 8/4/25 7:23 AM, Mohamed Mediouni wrote: > Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> > --- > hw/arm/virt.c | 3 + > hw/intc/arm_gicv3_common.c | 3 + > hw/intc/arm_gicv3_whpx.c | 261 +++++++++++++++++++++++++++++ > hw/intc/meson.build | 1 + > include/hw/intc/arm_gicv3_common.h | 3 + > 5 files changed, 271 insertions(+) > create mode 100644 hw/intc/arm_gicv3_whpx.c It would definitely needs another pair of eyes, which is more familiar with GIC topic, but patch looks good to me. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
On 8/4/25 7:23 AM, Mohamed Mediouni wrote:
> Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> ---
> hw/arm/virt.c | 3 +
> hw/intc/arm_gicv3_common.c | 3 +
> hw/intc/arm_gicv3_whpx.c | 261 +++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> include/hw/intc/arm_gicv3_common.h | 3 +
> 5 files changed, 271 insertions(+)
> create mode 100644 hw/intc/arm_gicv3_whpx.c
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 5951b331f3..98a1c74c42 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -49,6 +49,7 @@
> #include "system/tcg.h"
> #include "system/kvm.h"
> #include "system/hvf.h"
> +#include "system/whpx.h"
> #include "system/qtest.h"
> #include "hw/loader.h"
> #include "qapi/error.h"
> @@ -2060,6 +2061,8 @@ static void finalize_gic_version(VirtMachineState *vms)
> /* KVM w/o kernel irqchip can only deal with GICv2 */
> gics_supported |= VIRT_GIC_VERSION_2_MASK;
> accel_name = "KVM with kernel-irqchip=off";
> + } else if (whpx_enabled()) {
> + gics_supported |= VIRT_GIC_VERSION_3_MASK;
> } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
> gics_supported |= VIRT_GIC_VERSION_2_MASK;
> if (module_object_class_by_name("arm-gicv3")) {
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index e438d8c042..8b85b60c9b 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -32,6 +32,7 @@
> #include "gicv3_internal.h"
> #include "hw/arm/linux-boot-if.h"
> #include "system/kvm.h"
> +#include "system/whpx.h"
>
>
> static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
> @@ -662,6 +663,8 @@ const char *gicv3_class_name(void)
> {
> if (kvm_irqchip_in_kernel()) {
> return "kvm-arm-gicv3";
> + } else if (whpx_enabled()) {
> + return TYPE_WHPX_GICV3;
> } else {
> if (kvm_enabled()) {
> error_report("Userspace GICv3 is not supported with KVM");
> diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c
> new file mode 100644
> index 0000000000..ead4e167c5
> --- /dev/null
> +++ b/hw/intc/arm_gicv3_whpx.c
> @@ -0,0 +1,261 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * ARM Generic Interrupt Controller using HVF platform support
> + *
> + * Copyright (c) 2025 Mohamed Mediouni
> + * Based on vGICv3 KVM code by Pavel Fedin
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/intc/arm_gicv3_common.h"
> +#include "qemu/error-report.h"
> +#include "qemu/module.h"
> +#include "system/runstate.h"
> +#include "system/whpx.h"
> +#include "system/whpx-internal.h"
> +#include "gicv3_internal.h"
> +#include "vgic_common.h"
> +#include "qom/object.h"
> +#include "target/arm/cpregs.h"
> +
> +#include "hw/arm/bsa.h"
> +#include <winhvplatform.h>
> +#include <winhvplatformdefs.h>
> +#include <winnt.h>
> +
> +struct WHPXARMGICv3Class {
> + ARMGICv3CommonClass parent_class;
> + DeviceRealize parent_realize;
> + ResettablePhases parent_phases;
> +};
> +
> +typedef struct WHPXARMGICv3Class WHPXARMGICv3Class;
> +
> +/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */
> +DECLARE_OBJ_CHECKERS(GICv3State, WHPXARMGICv3Class,
> + WHPX_GICV3, TYPE_WHPX_GICV3);
> +
> +static void whpx_gicv3_check(GICv3State *s)
> +{
> +}
> +
> +static void whpx_gicv3_put_cpu(CPUState *cpu_state, run_on_cpu_data arg)
> +{
> +}
> +
> +static void whpx_gicv3_put(GICv3State *s)
> +{
> + int ncpu;
> +
> + whpx_gicv3_check(s);
> +
> + for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
> + run_on_cpu_data data;
> + data.host_ptr = &s->cpu[ncpu];
> + run_on_cpu(s->cpu[ncpu].cpu, whpx_gicv3_put_cpu, data);
> + }
> +}
> +
> +static void whpx_gicv3_get_cpu(CPUState *cpu_state, run_on_cpu_data arg)
> +{
> +}
> +
> +static void whpx_gicv3_get(GICv3State *s)
> +{
> + int ncpu;
> +
> + for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
> + run_on_cpu_data data;
> + data.host_ptr = &s->cpu[ncpu];
> + run_on_cpu(s->cpu[ncpu].cpu, whpx_gicv3_get_cpu, data);
> + }
> +}
> +
Probably a stupid question, but since check, get_cpu and put_cpu are
empty functions, why define them and the logic associated?
> +static void whpx_gicv3_set_irq(void *opaque, int irq, int level)
> +{
> + struct whpx_state *whpx = &whpx_global;
> +
> + GICv3State *s = (GICv3State *)opaque;
> + if (irq > s->num_irq) {
> + return;
> + }
> + WHV_INTERRUPT_TYPE interrupt_type = WHvArm64InterruptTypeFixed;
> + WHV_INTERRUPT_CONTROL interrupt_control = {
> + interrupt_type = WHvArm64InterruptTypeFixed,
> + .RequestedVector = GIC_INTERNAL + irq, .InterruptControl.Asserted = level};
> +
> + whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control,
> + sizeof(interrupt_control));
> +}
> +
> +static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + GICv3State *s;
> + GICv3CPUState *c;
> +
> + c = (GICv3CPUState *)env->gicv3state;
> + s = c->gic;
> +
> + c->icc_pmr_el1 = 0;
> + /*
> + * Architecturally the reset value of the ICC_BPR registers
> + * is UNKNOWN. We set them all to 0 here; when the kernel
> + * uses these values to program the ICH_VMCR_EL2 fields that
> + * determine the guest-visible ICC_BPR register values, the
> + * hardware's "writing a value less than the minimum sets
> + * the field to the minimum value" behaviour will result in
> + * them effectively resetting to the correct minimum value
> + * for the host GIC.
> + */
> + c->icc_bpr[GICV3_G0] = 0;
> + c->icc_bpr[GICV3_G1] = 0;
> + c->icc_bpr[GICV3_G1NS] = 0;
> +
> + c->icc_sre_el1 = 0x7;
> + memset(c->icc_apr, 0, sizeof(c->icc_apr));
> + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
> +
> + if (s->migration_blocker) {
> + return;
> + }
> +
> + c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
> +}
> +
> +static void whpx_gicv3_reset_hold(Object *obj, ResetType type)
> +{
> + GICv3State *s = ARM_GICV3_COMMON(obj);
> + WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s);
> +
> + if (kgc->parent_phases.hold) {
> + kgc->parent_phases.hold(obj, type);
> + }
> +
> + whpx_gicv3_put(s);
> +}
> +
> +
> +/*
> + * CPU interface registers of GIC needs to be reset on CPU reset.
> + * For the calling arm_gicv3_icc_reset() on CPU reset, we register
> + * below ARMCPRegInfo. As we reset the whole cpu interface under single
> + * register reset, we define only one register of CPU interface instead
> + * of defining all the registers.
> + */
> +static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
> + { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
> + /*
> + * If ARM_CP_NOP is used, resetfn is not called,
> + * So ARM_CP_NO_RAW is appropriate type.
> + */
> + .type = ARM_CP_NO_RAW,
> + .access = PL1_RW,
> + .readfn = arm_cp_read_zero,
> + .writefn = arm_cp_write_ignore,
> + /*
> + * We hang the whole cpu interface reset routine off here
> + * rather than parcelling it out into one little function
> + * per register
> + */
> + .resetfn = whpx_gicv3_icc_reset,
> + },
> +};
> +
> +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE val)
> +{
> + struct whpx_state *whpx = &whpx_global;
> + HRESULT hr;
> + hr = whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, cpu->cpu_index,
> + ®, 1, &val);
> +
> + if (FAILED(hr)) {
> + error_report("WHPX: Failed to set register %08x, hr=%08lx", reg, hr);
> + }
> +}
> +
> +static void whpx_gicv3_realize(DeviceState *dev, Error **errp)
> +{
> + GICv3State *s = WHPX_GICV3(dev);
> + WHPXARMGICv3Class *kgc = WHPX_GICV3_GET_CLASS(s);
> + Error *local_err = NULL;
> + int i;
> +
> + kgc->parent_realize(dev, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + if (s->revision != 3) {
> + error_setg(errp, "unsupported GIC revision %d for platform GIC",
> + s->revision);
> + }
> +
> + if (s->security_extn) {
> + error_setg(errp, "the platform vGICv3 does not implement the "
> + "security extensions");
> + return;
> + }
> +
> + if (s->nmi_support) {
> + error_setg(errp, "NMI is not supported with the platform GIC");
> + return;
> + }
> +
> + if (s->nb_redist_regions > 1) {
> + error_setg(errp, "Multiple VGICv3 redistributor regions are not "
> + "supported by WHPX");
> + error_append_hint(errp, "A maximum of %d VCPUs can be used",
> + s->redist_region_count[0]);
> + return;
> + }
> +
> + gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL);
> +
> + for (i = 0; i < s->num_cpu; i++) {
> + CPUState *cpu_state = qemu_get_cpu(i);
> + ARMCPU *cpu = ARM_CPU(cpu_state);
> + WHV_REGISTER_VALUE val = {.Reg64 = 0x080A0000 + (GICV3_REDIST_SIZE * i)};
> + whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val);
> + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
> + }
> +
> + if (s->maint_irq) {
> + error_setg(errp, "Nested virtualisation not currently supported by WHPX.");
> + return;
> + }
> +}
> +
> +static void whpx_gicv3_class_init(ObjectClass *klass, const void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> + ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
> + WHPXARMGICv3Class *kgc = WHPX_GICV3_CLASS(klass);
> +
> + agcc->pre_save = whpx_gicv3_get;
> + agcc->post_load = whpx_gicv3_put;
> +
> + device_class_set_parent_realize(dc, whpx_gicv3_realize,
> + &kgc->parent_realize);
> + resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NULL,
> + &kgc->parent_phases);
> +}
> +
> +static const TypeInfo whpx_arm_gicv3_info = {
> + .name = TYPE_WHPX_GICV3,
> + .parent = TYPE_ARM_GICV3_COMMON,
> + .instance_size = sizeof(GICv3State),
> + .class_init = whpx_gicv3_class_init,
> + .class_size = sizeof(WHPXARMGICv3Class),
> +};
> +
> +static void whpx_gicv3_register_types(void)
> +{
> + type_register_static(&whpx_arm_gicv3_info);
> +}
> +
> +type_init(whpx_gicv3_register_types)
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 3137521a4a..4fc6b78a04 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
> specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
> specific_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.c'))
> specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
> +specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('arm_gicv3_whpx.c'))
> specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
> specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
> specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
> diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
> index c18503869f..7776558a0e 100644
> --- a/include/hw/intc/arm_gicv3_common.h
> +++ b/include/hw/intc/arm_gicv3_common.h
> @@ -306,6 +306,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
> DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
> ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
>
> +/* Types for GICv3 kernel-irqchip */
> +#define TYPE_WHPX_GICV3 "whpx-arm-gicv3"
> +
> struct ARMGICv3CommonClass {
> /*< private >*/
> SysBusDeviceClass parent_class;
> On 4. Aug 2025, at 23:39, Pierrick Bouvier <pierrick.bouvier@linaro.org> wrote: > > Probably a stupid question, but since check, get_cpu and put_cpu are empty functions, why define them and the logic associated? They are empty today but won’t be once save/restore is implemented for the GICv3 state, which is still incomplete so that I carved it out of this patch series. That’s one of the last remaining blockers before VM save/restore -m
On 8/4/25 2:47 PM, Mohamed Mediouni wrote: > >> On 4. Aug 2025, at 23:39, Pierrick Bouvier >> <pierrick.bouvier@linaro.org> wrote: >> >> Probably a stupid question, but since check, get_cpu and put_cpu are >> empty functions, why define them and the logic associated? > > They are empty today but won’t be once save/restore is implemented for > the GICv3 state, which is still incomplete so that I carved it out of > this patch series. > > That’s one of the last remaining blockers before VM save/restore > I see thanks. Worth adding a comment into them for that. > -m
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