[PATCH 6/6] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid

Bibo Mao posted 6 patches 3 months, 1 week ago
There is a newer version of this series
[PATCH 6/6] target/loongarch: Only flush one TLB entry in helper_invtlb_page_asid
Posted by Bibo Mao 3 months, 1 week ago
With function helper_invtlb_page_asid(), one TLB entry in LoongArch
emulated TLB is invalidated if found. Also invalidate_tlb_entry()
can be called so that only one QEMU TLB entry will be flushed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/tcg/tlb_helper.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index c7f7c697af..70742691ab 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -551,7 +551,7 @@ void helper_invtlb_all_asid(CPULoongArchState *env, target_ulong info)
 void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
                              target_ulong addr)
 {
-    int index, asid = info & 0x3ff;
+    int index, asid = info & 0x3ff, csr_asid;
     LoongArchTLB *tlb;
     tlb_match func;
     bool ret;
@@ -562,9 +562,13 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
         return;
     }
 
+    csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
+    if (csr_asid == asid) {
+        invalidate_tlb_entry(env, index);
+    }
+
     tlb = &env->tlb[index];
     tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0);
-    tlb_flush(env_cpu(env));
 }
 
 void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
-- 
2.39.3