From: Smail AIDER via <qemu-devel@nongnu.org>

Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
accesses to the PMCR register to EL2.

Signed-off-by: Smail AIDER <smail.aider@huawei.com>
Message-Id: <20250722131925.2119169-1-smail.aider@huawei.com>
---
 target/arm/cpregs-pmu.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c
index 0f295b1376..3aacd4f652 100644
--- a/target/arm/cpregs-pmu.c
+++ b/target/arm/cpregs-pmu.c
@@ -252,6 +252,26 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
     return CP_ACCESS_OK;
 }
 
+/*
+ * Check for traps to PMCR register, which are controlled by PMUSERENR.EN
+ * for EL1, MDCR_EL2.TPM/TPMCR for EL2 and MDCR_EL3.TPM for EL3.
+ */
+static CPAccessResult pmreg_access_pmcr(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   bool isread)
+{
+    int el = arm_current_el(env);
+    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
+
+    CPAccessResult ret = pmreg_access(env, ri, isread);
+
+    /* Check MDCR_TPMCR if not already trapped to EL1 */
+    if (ret != CP_ACCESS_TRAP_EL1 && el < 2 && (mdcr_el2 & MDCR_TPMCR)) {
+        ret = CP_ACCESS_TRAP_EL2;
+    }
+
+    return ret;
+}
+
 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
                                            const ARMCPRegInfo *ri,
                                            bool isread)
@@ -1192,14 +1212,14 @@ void define_pm_cpregs(ARMCPU *cpu)
             .fgt = FGT_PMCR_EL0,
             .type = ARM_CP_IO | ARM_CP_ALIAS,
             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
-            .accessfn = pmreg_access,
+            .accessfn = pmreg_access_pmcr,
             .readfn = pmcr_read, .raw_readfn = raw_read,
             .writefn = pmcr_write, .raw_writefn = raw_write,
         };
         const ARMCPRegInfo pmcr64 = {
             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
-            .access = PL0_RW, .accessfn = pmreg_access,
+            .access = PL0_RW, .accessfn = pmreg_access_pmcr,
             .fgt = FGT_PMCR_EL0,
             .type = ARM_CP_IO,
             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
-- 
2.34.1

On 01.08.2025 12:06, Smail AIDER via wrote:
> From: Smail AIDER via <qemu-devel@nongnu.org>
> 
> Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
> Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
> accesses to the PMCR register to EL2.
> 
> Signed-off-by: Smail AIDER <smail.aider@huawei.com>
> Message-Id: <20250722131925.2119169-1-smail.aider@huawei.com>

I'm assuming this is for qemu-stable too (Cc'ed), just like the
v1 of this patch was.  Please let me know it it isn't.

Thanks,

/mjt

Yes, this patch is also intended to qemu-stable.

Thank you.

--
Best Regards,
Smail AIDER
E-Mail: smail.aider@huawei.com
Operating System Researcher/Developer
Dresden Research Center, OS Kernel Lab
Huawei Technologies Co., Ltd

-----Original Message-----
From: Michael Tokarev <mjt@tls.msk.ru> 
Sent: Sunday, August 10, 2025 4:41 PM
To: Smail AIDER <smail.aider@huawei.com>; qemu-devel@nongnu.org
Cc: Alexander Spyridakis <alexander.spyridakis@huawei.com>; qemu-arm@nongnu.org; Peter Maydell <peter.maydell@linaro.org>; zhangyue (BA) <zhangyue165@huawei.com>; richard.henderson@linaro.org; Liuyutao(DRC) <liuyutao2@huawei.com>; qemu-stable <qemu-stable@nongnu.org>
Subject: Re: [PATCH v2 1/2] target/arm: Trap PMCR when MDCR_EL2.TPMCR is set

On 01.08.2025 12:06, Smail AIDER via wrote:
> From: Smail AIDER via <qemu-devel@nongnu.org>
> 
> Trap PMCR_EL0 or PMCR accesses to EL2 when MDCR_EL2.TPMCR is set.
> Similar to MDCR_EL2.TPM, MDCR_EL2.TPMCR allows trapping EL0 and EL1
> accesses to the PMCR register to EL2.
> 
> Signed-off-by: Smail AIDER <smail.aider@huawei.com>
> Message-Id: <20250722131925.2119169-1-smail.aider@huawei.com>

I'm assuming this is for qemu-stable too (Cc'ed), just like the
v1 of this patch was.  Please let me know it it isn't.

Thanks,

/mjt