There is some enhance about LoongArch mmu tcg emulation, add new
header file cpu-mmu.h and function loongarch_check_pte(). Function
loongarch_check_pte() can work on both TLB entry and pte entry.

This patchset mainly is code cleanup and enhancement, its main
purpose is to work for hardware page table walk emluation in future.
---
v2 ... v3:
  1. Track user space page accessed in kernel mode, since mmu idx usage
     is different between QEMU TLB and LoongArch TLB emulation.
  2. Add 48 bit to 64 bit signed extension conversion with virtual address,
     since QEMU TLB use 64 bit address, LoongArch TLB is 48 bit.
  3. Optimization with LoongArch TLB update, do not flush QEMU TLB if
     updated TLB entry is the same or invalid.
  4. Optimization with new LoongArch TLB entry selection, invalid entry
     or different ASID with higher priority than the random method.
v1 ... v2:
  1. Rename structure name pte_context with mmu_context, since it
     can be extended to get DMW or DA mmu idx and window size
  2. Add fine-grained tlb flush method
  3. Fix some issues in function invalidate_tlb_entry() to flush tlb,
     such as bitmap method with mmu idx, page size and address
     calculation
---
Bibo Mao (17):
  target/loongarch: Move some function definition to kvm directory
  target/loongarch: Define function loongarch_cpu_post_init as static
  target/loongarch: Set page size in TLB misc with STLB
  target/loongarch: Add header file cpu-mmu.h
  target/loongarch: Add common function loongarch_check_pte()
  target/loongarch: Use loongarch_check_pte() with page table walking
  target/loongarch: Add parameter mmu_context with
    loongarch_page_table_walker
  target/loongarch: Add parameter mmu_context with
    loongarch_map_tlb_entry
  target/loongarch: Add parameter mmu_context with
    loongarch_get_addr_from_tlb
  target/loongarch: Add parameter mmu_context with loongarch_map_address
  target/loongarch: Add parameter mmu_context with get_physical_address
  target/loongarch: Track user mode address accessed in kernel mode
  target/loongarch: Use correct address when flush tlb
  target/loongarch: Use mmu idx bitmap method when flush tlb
  target/loongarch: Add parameter tlb pointer with fill_tlb_entry
  target/loongarch: Reduce TLB flush with helper_tlbwr
  target/loongarch: Update TLB index selection method

 hw/loongarch/virt.c                  |   1 +
 target/loongarch/cpu-mmu.h           |  41 ++++
 target/loongarch/cpu.c               | 181 +++++++++---------
 target/loongarch/cpu.h               |  22 +--
 target/loongarch/cpu_helper.c        | 131 ++++++++-----
 target/loongarch/internals.h         |  20 --
 target/loongarch/kvm/kvm_loongarch.h |   4 +-
 target/loongarch/tcg/csr_helper.c    |   1 +
 target/loongarch/tcg/tcg_loongarch.h |   4 +-
 target/loongarch/tcg/tlb_helper.c    | 272 ++++++++++++++++-----------
 10 files changed, 395 insertions(+), 282 deletions(-)
 create mode 100644 target/loongarch/cpu-mmu.h


base-commit: 9e601684dc24a521bb1d23215a63e5c6e79ea0bb
-- 
2.39.3