[v1] intc/riscv_aplic: Fix target register read when source is inactive

[PATCH v1] intc/riscv_aplic: Fix target register read when source is inactive

Posted by Yang Jialong 4 months, 4 weeks ago

The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.

Signed-off-by: Yang Jialong <z_bajeer@yeah.net>
---
 hw/intc/riscv_aplic.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4fa5f75..cfef69f 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
 
 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
 {
-    uint32_t irq, word, idc;
+    uint32_t irq, word, idc, sm;
     RISCVAPLICState *aplic = opaque;
 
     /* Reads must be 4 byte words */
@@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
     } else if ((APLIC_TARGET_BASE <= addr) &&
             (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
         irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
+        sm = aplic->sourcecfg[irq] * APLIC_SOURCECFG_SM_MASK;
+        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
+            return 0;
+        }
         return aplic->target[irq];
     } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
             (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {
-- 
2.34.1

Re: [PATCH v1] intc/riscv_aplic: Fix target register read when source is inactive

Posted by Daniel Henrique Barboza 4 months, 3 weeks ago


On 7/24/25 6:34 AM, Yang Jialong wrote:
> The RISC-V Advanced interrupt Architecture:
> 4.5.16. Interrupt targets:
> If interrupt source i is inactive in this domain, register target[i] is
> read-only zero.
> 
> Signed-off-by: Yang Jialong <z_bajeer@yeah.net>
> ---
>   hw/intc/riscv_aplic.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 4fa5f75..cfef69f 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
>   
>   static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
>   {
> -    uint32_t irq, word, idc;
> +    uint32_t irq, word, idc, sm;
>       RISCVAPLICState *aplic = opaque;
>   
>       /* Reads must be 4 byte words */
> @@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
>       } else if ((APLIC_TARGET_BASE <= addr) &&
>               (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
>           irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
> +        sm = aplic->sourcecfg[irq] * APLIC_SOURCECFG_SM_MASK;

I believe you want '&' here:


sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;

Otherwise, given that APLIC_SOURCECFG_SM_INACTIVE is 0x0, the only way

sm == APLIC_SOURCECFG_SM_INACTIVE

will happen is aplic->sourcecfg[irq] being 0.


Thanks,

Daniel

> +        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
> +            return 0;
> +        }
>           return aplic->target[irq];
>       } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
>               (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {

回复: [PATCH v1] intc/riscv_aplic: Fix target register read when source is inactive

Posted by z_bajeer@yeah.net 4 months, 3 weeks ago

> On 7/24/25 6:34 AM, Yang Jialong wrote:
> > The RISC-V Advanced interrupt Architecture:
> > 4.5.16. Interrupt targets:
> > If interrupt source i is inactive in this domain, register target[i] is
> > read-only zero.
> > 
> > Signed-off-by: Yang Jialong <z_bajeer@yeah.net>
> > ---
> >   hw/intc/riscv_aplic.c | 6 +++++-
> >   1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> > index 4fa5f75..cfef69f 100644
> > --- a/hw/intc/riscv_aplic.c
> > +++ b/hw/intc/riscv_aplic.c
> > @@ -628,7 +628,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
> >   
> >   static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
> >   {
> > -    uint32_t irq, word, idc;
> > +    uint32_t irq, word, idc, sm;
> >       RISCVAPLICState *aplic = opaque;
> >   
> >       /* Reads must be 4 byte words */
> > @@ -696,6 +696,10 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)
> >       } else if ((APLIC_TARGET_BASE <= addr) &&
> >               (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {
> >           irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;
> > +        sm = aplic->sourcecfg[irq] * APLIC_SOURCECFG_SM_MASK;
> 
> I believe you want '&' here:
> 

... Yes. Thanks. I will submit a newer one.

> 
> sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK;
> 
> Otherwise, given that APLIC_SOURCECFG_SM_INACTIVE is 0x0, the only way
> 
> sm == APLIC_SOURCECFG_SM_INACTIVE
> 
> will happen is aplic->sourcecfg[irq] being 0.
> 
> 
> Thanks,
> 
> Daniel
> 
> > +        if (sm == APLIC_SOURCECFG_SM_INACTIVE) {
> > +            return 0;
> > +        }
> >           return aplic->target[irq];
> >       } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&
> >               (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {