On Tue, 22 Jul 2025 at 15:24, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Hi Peter,
>
> Sadly, I couldn't reorg mtedesc as I hypothesized, because of
> different usage within AdvSIMD. So I decided to expand the
> mtedesc from 17 to 32 bits, and then pack the gvec desc and
> mtedesc into a 64-bit argument.
I was playing around with this today as well, and I
did manage to get something that seems to work with an
msz/nregs split. I opted to just re-encode the byte
length back into a fake msz/nregs combo in gen_mte_checkN,
which is the main place we don't already have an actual msz/nregs:
+ /*
+ * Encode the total_size into how we fit it into an MTEDESC
+ * and assert that it fits, whether MTE is enabled or not.
+ */
+ uint32_t nregs;
+
+ if (((total_size / 3) * 3) == total_size) {
+ /* If this is a multiple of 3, we need to use that for nregs */
+ total_size /= 3;
+ nregs = 3;
+ } else {
+ /* Use the highest of nregs = 4 / 2 / 1 that we can */
+ switch (ctz32(total_size)) {
+ case 0:
+ nregs = 1;
+ break;
+ case 1:
+ total_size >>= 1;
+ nregs = 2;
+ break;
+ default:
+ total_size >>= 2;
+ nregs = 4;
+ break;
+ }
+ }
+ /* Now we've divided by our chosen nregs we must have a valid MO_* */
+ assert(is_power_of_2(total_size));
+ assert(total_size >= 1 && total_size <= (1 << MO_SIZE));
But I think your approach is better because it's more
straightforward, and it means we will have space space in
MTEDESC for future purposes.
> Lightly tested so far, but it does fix the LD3Q/LD4Q assert.
There's also a bug we have at the moment where gen_sve_ldr()
and gen_sve_str() call gen_mte_checkN() with a length value
which is the SVE vector length and can be up to 256 bytes.
We don't assert there, so we just fail to do the MTE checks
on the right length of memory. I assume these patches will
fix that too.
thanks
-- PMM