From: Nicholas Piggin <npiggin@gmail.com>
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Tested-by: Gautam Menghani <gautam@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-35-npiggin@gmail.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/intc/xive.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 119a178f2e23..db26dae7dbf4 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0);
g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0);
- qemu_irq_lower(xive_tctx_output(tctx, sig_ring));
-
if (xive_nsr_indicates_exception(sig_ring, nsr)) {
uint8_t cppr = sig_regs[TM_PIPR];
uint8_t ring;
@@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
/* Clear the exception from NSR */
sig_regs[TM_NSR] = 0;
+ qemu_irq_lower(xive_tctx_output(tctx, sig_ring));
trace_xive_tctx_accept(tctx->cs->cpu_index, ring,
regs[TM_IPB], sig_regs[TM_PIPR],
--
2.50.1