[v6] riscv: Add support for MIPS P8700 CPU

[PATCH v6 03/14] target/riscv: Add MIPS P8700 CPU

Posted by Djordje Todorovic 2 months, 2 weeks ago

Introduce P8700 CPU by MIPS.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu-qom.h      |  1 +
 target/riscv/cpu.c          | 15 +++++++++++++++
 target/riscv/cpu_vendorid.h |  1 +
 3 files changed, 17 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 1ee05eb393..1e62b96094 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -55,6 +55,7 @@
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
 #define TYPE_RISCV_CPU_TT_ASCALON       RISCV_CPU_TYPE_NAME("tt-ascalon")
 #define TYPE_RISCV_CPU_XIANGSHAN_NANHU  RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
+#define TYPE_RISCV_CPU_MIPS_P8700       RISCV_CPU_TYPE_NAME("mips-p8700")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e584bdc5ac..401c0f6c7d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3180,6 +3180,21 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .cfg.max_satp_mode = VM_1_10_SV39,
     ),
 
+    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
+        .misa_mxl_max = MXL_RV64,
+        .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
+        .priv_spec = PRIV_VERSION_1_12_0,
+        .cfg.max_satp_mode = VM_1_10_SV48,
+        .cfg.ext_zifencei = true,
+        .cfg.ext_zicsr = true,
+        .cfg.mmu = true,
+        .cfg.pmp = true,
+        .cfg.ext_zba = true,
+        .cfg.ext_zbb = true,
+        .cfg.marchid = 0x8000000000000201,
+        .cfg.mvendorid = MIPS_VENDOR_ID,
+    ),
+
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
     DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
         .cfg.max_satp_mode = VM_1_10_SV57,
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
index 96b6b9c2cb..28f0ce9370 100644
--- a/target/riscv/cpu_vendorid.h
+++ b/target/riscv/cpu_vendorid.h
@@ -2,6 +2,7 @@
 #define TARGET_RISCV_CPU_VENDORID_H
 
 #define THEAD_VENDOR_ID         0x5b7
+#define MIPS_VENDOR_ID          0x722
 
 #define VEYRON_V1_MARCHID       0x8000000000010000
 #define VEYRON_V1_MIMPID        0x111
-- 
2.34.1

Re: [PATCH v6 03/14] target/riscv: Add MIPS P8700 CPU

Posted by Philippe Mathieu-Daudé 1 month, 3 weeks ago

On 17/7/25 11:38, Djordje Todorovic wrote:
> Introduce P8700 CPU by MIPS.
> 
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
>   target/riscv/cpu-qom.h      |  1 +
>   target/riscv/cpu.c          | 15 +++++++++++++++
>   target/riscv/cpu_vendorid.h |  1 +
>   3 files changed, 17 insertions(+)


> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e584bdc5ac..401c0f6c7d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3180,6 +3180,21 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.max_satp_mode = VM_1_10_SV39,
>       ),
>   

Can we add the datasheet link here?

        /* https://mips.com/products/hardware/p8700/ */

> +    DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
> +        .misa_mxl_max = MXL_RV64,
> +        .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
> +        .priv_spec = PRIV_VERSION_1_12_0,
> +        .cfg.max_satp_mode = VM_1_10_SV48,
> +        .cfg.ext_zifencei = true,
> +        .cfg.ext_zicsr = true,
> +        .cfg.mmu = true,
> +        .cfg.pmp = true,
> +        .cfg.ext_zba = true,
> +        .cfg.ext_zbb = true,
> +        .cfg.marchid = 0x8000000000000201,
> +        .cfg.mvendorid = MIPS_VENDOR_ID,
> +    ),

Re: [PATCH v6 03/14] target/riscv: Add MIPS P8700 CPU

Posted by Djordje Todorovic 4 weeks ago

On 8. 8. 25. 19:02, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do 
> not click links or open attachments unless you recognize the sender 
> and know the content is safe.
>
>
> On 17/7/25 11:38, Djordje Todorovic wrote:
>> Introduce P8700 CPU by MIPS.
>>
>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> ---
>>   target/riscv/cpu-qom.h      |  1 +
>>   target/riscv/cpu.c          | 15 +++++++++++++++
>>   target/riscv/cpu_vendorid.h |  1 +
>>   3 files changed, 17 insertions(+)
>
>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index e584bdc5ac..401c0f6c7d 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -3180,6 +3180,21 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>>           .cfg.max_satp_mode = VM_1_10_SV39,
>>       ),
>>
>
> Can we add the datasheet link here?
>
>        /* https://mips.com/products/hardware/p8700/ */
>
Yes, I will add it in v7.


>> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
>> +        .misa_mxl_max = MXL_RV64,
>> +        .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
>> +        .priv_spec = PRIV_VERSION_1_12_0,
>> +        .cfg.max_satp_mode = VM_1_10_SV48,
>> +        .cfg.ext_zifencei = true,
>> +        .cfg.ext_zicsr = true,
>> +        .cfg.mmu = true,
>> +        .cfg.pmp = true,
>> +        .cfg.ext_zba = true,
>> +        .cfg.ext_zbb = true,
>> +        .cfg.marchid = 0x8000000000000201,
>> +        .cfg.mvendorid = MIPS_VENDOR_ID,
>> +    ),
>