Hi Daniel,
Thank you for your comments!
I will follow this.
Best,
Djordje
On 7. 8. 25. 20:35, Daniel Henrique Barboza wrote:
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>
>
> Hi,
>
> I have provided reviews and acks on the v4 review:
>
> https://lore.kernel.org/qemu-riscv/20250625141732.59084-1-djordje.todorovic@htecgroup.com/
>
>
> I also gave one additional ack/review in patch 8 in v5:
>
> https://lore.kernel.org/qemu-riscv/20250703104925.112688-1-djordje.todorovic@htecgroup.com/
>
>
> I see no acks in any patches in this version.
>
> The common practice is to include any reviewed-by/acked-by tags
> received in the commit
> msg of each patch when submitting a new version, letting other ppl
> know that the patch
> was already looked at once. Unless you make changes in the patch and
> the review gave
> before is now invalid - then in this case you drop the tag and a new
> review is
> required.
>
> Unless you completely changed all the patches and all the reviews
> doesn't apply
> anymore, please re-send this series with the acks/reviewed-by tags in
> the patches.
> From my estimation this series is supposed to have 2-3 patches missing
> review only.
>
>
> Thanks,
>
> Daniel
>
>
>
>
> On 7/17/25 6:38 AM, Djordje Todorovic wrote:
>> I addressed several comments in this version, major ones:
>> - split CPC / CMGCR into separated changes
>> - split CPS into a separated change
>> - added functional tests for boston-aia board
>>
>> Djordje Todorovic (14):
>> hw/intc: Allow gaps in hartids for aclint and aplic
>> target/riscv: Add cpu_set_exception_base
>> target/riscv: Add MIPS P8700 CPU
>> target/riscv: Add MIPS P8700 CSRs
>> target/riscv: Add mips.ccmov instruction
>> target/riscv: Add mips.pref instruction
>> target/riscv: Add Xmipslsp instructions
>> hw/misc: Add RISC-V CMGCR device implementation
>> hw/misc: Add RISC-V CPC device implementation
>> hw/riscv: Add support for RISCV CPS
>> hw/riscv: Add support for MIPS Boston-aia board mode
>> hw/pci: Allow explicit function numbers in pci
>> riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
>> test/functional: Add test for boston-aia board
>>
>> configs/devices/riscv64-softmmu/default.mak | 1 +
>> docs/system/riscv/mips.rst | 20 +
>> docs/system/target-riscv.rst | 1 +
>> hw/intc/riscv_aclint.c | 21 +-
>> hw/intc/riscv_aplic.c | 11 +-
>> hw/misc/Kconfig | 20 +
>> hw/misc/meson.build | 3 +
>> hw/misc/riscv_cmgcr.c | 234 ++++++++++
>> hw/misc/riscv_cpc.c | 239 ++++++++++
>> hw/pci/pci.c | 15 +-
>> hw/riscv/Kconfig | 6 +
>> hw/riscv/boston-aia.c | 489 ++++++++++++++++++++
>> hw/riscv/cps.c | 197 ++++++++
>> hw/riscv/meson.build | 3 +
>> include/hw/misc/riscv_cmgcr.h | 49 ++
>> include/hw/misc/riscv_cpc.h | 73 +++
>> include/hw/riscv/cps.h | 76 +++
>> target/riscv/cpu-qom.h | 1 +
>> target/riscv/cpu.c | 40 ++
>> target/riscv/cpu.h | 7 +
>> target/riscv/cpu_cfg.h | 6 +
>> target/riscv/cpu_cfg_fields.h.inc | 3 +
>> target/riscv/cpu_vendorid.h | 1 +
>> target/riscv/insn_trans/trans_xmips.c.inc | 142 ++++++
>> target/riscv/meson.build | 2 +
>> target/riscv/mips_csr.c | 228 +++++++++
>> target/riscv/translate.c | 3 +
>> target/riscv/xmips.decode | 35 ++
>> tests/functional/meson.build | 1 +
>> tests/functional/test_riscv64_boston.py | 78 ++++
>> 30 files changed, 1994 insertions(+), 11 deletions(-)
>> create mode 100644 docs/system/riscv/mips.rst
>> create mode 100644 hw/misc/riscv_cmgcr.c
>> create mode 100644 hw/misc/riscv_cpc.c
>> create mode 100644 hw/riscv/boston-aia.c
>> create mode 100644 hw/riscv/cps.c
>> create mode 100644 include/hw/misc/riscv_cmgcr.h
>> create mode 100644 include/hw/misc/riscv_cpc.h
>> create mode 100644 include/hw/riscv/cps.h
>> create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>> create mode 100644 target/riscv/mips_csr.c
>> create mode 100644 target/riscv/xmips.decode
>> create mode 100755 tests/functional/test_riscv64_boston.py
>>
>