On Wed, Jul 16, 2025 at 11:54:27AM +0200, Luc Michel wrote:
> Update the list of supported devices in the Versal SoCs.
>
> Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
> ---
> docs/system/arm/xlnx-versal-virt.rst | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
> index 2c63fbf519f..94c8bacf61a 100644
> --- a/docs/system/arm/xlnx-versal-virt.rst
> +++ b/docs/system/arm/xlnx-versal-virt.rst
> @@ -21,15 +21,15 @@ The AMD Versal Virt board in QEMU is a model of a virtual board
> (does not exist in reality) with a virtual Versal SoC without I/O
> limitations. Currently, we support the following cores and devices:
>
> Implemented CPU cores:
>
> -- 2 ACPUs (ARM Cortex-A72)
> +- 2 ACPUs (ARM Cortex-A72) with their GICv3 and ITS
> +- 2 RCPUs (ARM Cortex-R5F) with their GICv2
>
> Implemented devices:
>
> -- Interrupt controller (ARM GICv3)
> - 2 UARTs (ARM PL011)
> - An RTC (Versal built-in)
> - 2 GEMs (Cadence MACB Ethernet MACs)
> - 8 ADMA (Xilinx zDMA) channels
> - 2 SD Controllers
> @@ -37,10 +37,13 @@ Implemented devices:
> - XRAM (4MB of on chip Accelerator RAM)
> - DDR memory
> - BBRAM (36 bytes of Battery-backed RAM)
> - eFUSE (3072 bytes of one-time field-programmable bit array)
> - 2 CANFDs
> +- USB controller
> +- OSPI controller
> +- TRNG controller
>
> QEMU does not yet model any other devices, including the PL and the AI Engine.
>
> Other differences between the hardware and the QEMU model:
>
> --
> 2.50.0
>