[v1] AMD Versal Gen 2 support

[PATCH 01/48] hw/net/cadence_gem: fix register mask initialization

Posted by Luc Michel 6 months, 4 weeks ago

The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.

Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt registers")
Signed-off-by: Luc Michel <luc.michel@amd.com>
---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 50025d5a6f2..44446666deb 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1754,10 +1754,11 @@ static void gem_realize(DeviceState *dev, Error **errp)
 
     for (i = 0; i < s->num_priority_queues; ++i) {
         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
     }
 
+    gem_init_register_masks(s);
     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 
     s->nic = qemu_new_nic(&net_gem_info, &s->conf,
                           object_get_typename(OBJECT(dev)), dev->id,
                           &dev->mem_reentrancy_guard, s);
@@ -1774,11 +1775,10 @@ static void gem_init(Object *obj)
     CadenceGEMState *s = CADENCE_GEM(obj);
     DeviceState *dev = DEVICE(obj);
 
     DB_PRINT("\n");
 
-    gem_init_register_masks(s);
     memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
                           "enet", sizeof(s->regs));
 
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 }
-- 
2.50.0

RE: [PATCH 01/48] hw/net/cadence_gem: fix register mask initialization

Posted by Boddu, Sai Pavan 6 months, 2 weeks ago

[AMD Official Use Only - AMD Internal Distribution Only]

>-----Original Message-----
>From: Luc Michel <luc.michel@amd.com>
>Sent: Wednesday, July 16, 2025 3:24 PM
>To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
>Cc: Michel, Luc <Luc.Michel@amd.com>; Peter Maydell
><peter.maydell@linaro.org>; Iglesias, Francisco <francisco.iglesias@amd.com>;
>Iglesias, Edgar <Edgar.Iglesias@amd.com>; Philippe Mathieu-Daudé
><philmd@linaro.org>; Alistair Francis <alistair@alistair23.me>; Konrad, Frederic
><Frederic.Konrad@amd.com>; Boddu, Sai Pavan <sai.pavan.boddu@amd.com>;
>Jason Wang <jasowang@redhat.com>
>Subject: [PATCH 01/48] hw/net/cadence_gem: fix register mask initialization
>
>The gem_init_register_masks function was called at init time but it relies on the num-
>priority-queues property. Call it at realize time instead.
>
>Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt
>registers")
>Signed-off-by: Luc Michel <luc.michel@amd.com>

Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>

>---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
>50025d5a6f2..44446666deb 100644
>--- a/hw/net/cadence_gem.c
>+++ b/hw/net/cadence_gem.c
>@@ -1754,10 +1754,11 @@ static void gem_realize(DeviceState *dev, Error **errp)
>
>     for (i = 0; i < s->num_priority_queues; ++i) {
>         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
>     }
>
>+    gem_init_register_masks(s);
>     qemu_macaddr_default_if_unset(&s->conf.macaddr);
>
>     s->nic = qemu_new_nic(&net_gem_info, &s->conf,
>                           object_get_typename(OBJECT(dev)), dev->id,
>                           &dev->mem_reentrancy_guard, s); @@ -1774,11 +1775,10 @@
>static void gem_init(Object *obj)
>     CadenceGEMState *s = CADENCE_GEM(obj);
>     DeviceState *dev = DEVICE(obj);
>
>     DB_PRINT("\n");
>
>-    gem_init_register_masks(s);
>     memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
>                           "enet", sizeof(s->regs));
>
>     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);  }
>--
>2.50.0

Re: [PATCH 01/48] hw/net/cadence_gem: fix register mask initialization

Posted by Francisco Iglesias 6 months, 2 weeks ago

On Wed, Jul 16, 2025 at 11:53:43AM +0200, Luc Michel wrote:
> The gem_init_register_masks function was called at init time but it
> relies on the num-priority-queues property. Call it at realize time
> instead.
> 
> Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt registers")
> Signed-off-by: Luc Michel <luc.michel@amd.com>

Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>


> ---
>  hw/net/cadence_gem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 50025d5a6f2..44446666deb 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1754,10 +1754,11 @@ static void gem_realize(DeviceState *dev, Error **errp)
>  
>      for (i = 0; i < s->num_priority_queues; ++i) {
>          sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
>      }
>  
> +    gem_init_register_masks(s);
>      qemu_macaddr_default_if_unset(&s->conf.macaddr);
>  
>      s->nic = qemu_new_nic(&net_gem_info, &s->conf,
>                            object_get_typename(OBJECT(dev)), dev->id,
>                            &dev->mem_reentrancy_guard, s);
> @@ -1774,11 +1775,10 @@ static void gem_init(Object *obj)
>      CadenceGEMState *s = CADENCE_GEM(obj);
>      DeviceState *dev = DEVICE(obj);
>  
>      DB_PRINT("\n");
>  
> -    gem_init_register_masks(s);
>      memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
>                            "enet", sizeof(s->regs));
>  
>      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
>  }
> -- 
> 2.50.0
>