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[PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost

zhangzhijie posted 1 patch 4 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250715064400.2289152-1-zhangzhijie@bosc.ac.cn
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Andrey Smirnov <andrew.smirnov@gmail.com>
hw/pci-host/designware.c         | 12 +++++++++---
include/hw/pci-host/designware.h |  2 +-
2 files changed, 10 insertions(+), 4 deletions(-)
[PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost
Posted by zhangzhijie 4 months ago 
0. DW pcie support 64bit resource
1. DW version type using Linux kernel

Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
---
 hw/pci-host/designware.c         | 12 +++++++++---
 include/hw/pci-host/designware.h |  2 +-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index f6e49ce9b8..99d791c0a7 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -41,6 +41,8 @@
 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
 #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
+#define PCIE_VERSION_NUMBER                        0x8F8
+#define PCIE_VERSION_TYPE                          0x8FC
 #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
 #define DESIGNWARE_PCIE_ATU_CR1                    0x904
@@ -144,6 +146,10 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
     uint32_t val;
 
     switch (address) {
+    case PCIE_VERSION_NUMBER:
+    case PCIE_VERSION_TYPE:
+        val = 0x3534302a;
+        break;
     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
         /*
          * Linux guest uses this register only to configure number of
@@ -427,7 +433,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
         viewport->inbound = true;
         viewport->base    = 0x0000000000000000ULL;
         viewport->target  = 0x0000000000000000ULL;
-        viewport->limit   = UINT32_MAX;
+        viewport->limit   = UINT64_MAX;
         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
 
         source      = &host->pci.address_space_root;
@@ -451,7 +457,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
         viewport->inbound = false;
         viewport->base    = 0x0000000000000000ULL;
         viewport->target  = 0x0000000000000000ULL;
-        viewport->limit   = UINT32_MAX;
+        viewport->limit   = UINT64_MAX;
         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
 
         destination = &host->pci.memory;
@@ -558,7 +564,7 @@ static const VMStateDescription vmstate_designware_pcie_viewport = {
     .fields = (const VMStateField[]) {
         VMSTATE_UINT64(base, DesignwarePCIEViewport),
         VMSTATE_UINT64(target, DesignwarePCIEViewport),
-        VMSTATE_UINT32(limit, DesignwarePCIEViewport),
+        VMSTATE_UINT64(limit, DesignwarePCIEViewport),
         VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
         VMSTATE_END_OF_LIST()
     }
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index a35a3bd06c..6e06f54801 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -46,7 +46,7 @@ typedef struct DesignwarePCIEViewport {
 
     uint64_t base;
     uint64_t target;
-    uint32_t limit;
+    uint64_t limit;
     uint32_t cr[2];
 
     bool inbound;
-- 
2.34.1
Re: [PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost
Posted by Bernhard Beschow 4 months ago 

Am 15. Juli 2025 06:44:00 UTC schrieb zhangzhijie <zhangzhijie@bosc.ac.cn>:
>0. DW pcie support 64bit resource
>1. DW version type using Linux kernel

Which machines in QEMU require this change?

>
>Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
>---
> hw/pci-host/designware.c         | 12 +++++++++---
> include/hw/pci-host/designware.h |  2 +-
> 2 files changed, 10 insertions(+), 4 deletions(-)
>
>diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>index f6e49ce9b8..99d791c0a7 100644
>--- a/hw/pci-host/designware.c
>+++ b/hw/pci-host/designware.c
>@@ -41,6 +41,8 @@
> #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
> #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
> #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
>+#define PCIE_VERSION_NUMBER                        0x8F8
>+#define PCIE_VERSION_TYPE                          0x8FC
> #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
> #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
> #define DESIGNWARE_PCIE_ATU_CR1                    0x904
>@@ -144,6 +146,10 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
>     uint32_t val;
> 
>     switch (address) {
>+    case PCIE_VERSION_NUMBER:
>+    case PCIE_VERSION_TYPE:
>+        val = 0x3534302a;
>+        break;
>     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
>         /*
>          * Linux guest uses this register only to configure number of
>@@ -427,7 +433,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>         viewport->inbound = true;
>         viewport->base    = 0x0000000000000000ULL;
>         viewport->target  = 0x0000000000000000ULL;
>-        viewport->limit   = UINT32_MAX;
>+        viewport->limit   = UINT64_MAX;
>         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
> 
>         source      = &host->pci.address_space_root;
>@@ -451,7 +457,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>         viewport->inbound = false;
>         viewport->base    = 0x0000000000000000ULL;
>         viewport->target  = 0x0000000000000000ULL;
>-        viewport->limit   = UINT32_MAX;
>+        viewport->limit   = UINT64_MAX;
>         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
> 
>         destination = &host->pci.memory;
>@@ -558,7 +564,7 @@ static const VMStateDescription vmstate_designware_pcie_viewport = {
>     .fields = (const VMStateField[]) {
>         VMSTATE_UINT64(base, DesignwarePCIEViewport),
>         VMSTATE_UINT64(target, DesignwarePCIEViewport),
>-        VMSTATE_UINT32(limit, DesignwarePCIEViewport),
>+        VMSTATE_UINT64(limit, DesignwarePCIEViewport),
>         VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
>         VMSTATE_END_OF_LIST()
>     }
>diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
>index a35a3bd06c..6e06f54801 100644
>--- a/include/hw/pci-host/designware.h
>+++ b/include/hw/pci-host/designware.h
>@@ -46,7 +46,7 @@ typedef struct DesignwarePCIEViewport {
> 
>     uint64_t base;
>     uint64_t target;
>-    uint32_t limit;
>+    uint64_t limit;
>     uint32_t cr[2];
> 
>     bool inbound;
Re: [PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost
Posted by zhangzhijie 4 months ago 

在 2025/7/17 1:53, Bernhard Beschow 写道:
> 
> 
> Am 15. Juli 2025 06:44:00 UTC schrieb zhangzhijie <zhangzhijie@bosc.ac.cn>:
>> 0. DW pcie support 64bit resource
>> 1. DW version type using Linux kernel
> 
> Which machines in QEMU require this change?
> 
after support 64bit resource, will support on riscv
>>
>> Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
>> ---
>> hw/pci-host/designware.c         | 12 +++++++++---
>> include/hw/pci-host/designware.h |  2 +-
>> 2 files changed, 10 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>> index f6e49ce9b8..99d791c0a7 100644
>> --- a/hw/pci-host/designware.c
>> +++ b/hw/pci-host/designware.c
>> @@ -41,6 +41,8 @@
>> #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
>> #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
>> #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
>> +#define PCIE_VERSION_NUMBER                        0x8F8
>> +#define PCIE_VERSION_TYPE                          0x8FC
>> #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
>> #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
>> #define DESIGNWARE_PCIE_ATU_CR1                    0x904
>> @@ -144,6 +146,10 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
>>      uint32_t val;
>>
>>      switch (address) {
>> +    case PCIE_VERSION_NUMBER:
>> +    case PCIE_VERSION_TYPE:
>> +        val = 0x3534302a;
>> +        break;
>>      case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
>>          /*
>>           * Linux guest uses this register only to configure number of
>> @@ -427,7 +433,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>>          viewport->inbound = true;
>>          viewport->base    = 0x0000000000000000ULL;
>>          viewport->target  = 0x0000000000000000ULL;
>> -        viewport->limit   = UINT32_MAX;
>> +        viewport->limit   = UINT64_MAX;
>>          viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
>>
>>          source      = &host->pci.address_space_root;
>> @@ -451,7 +457,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>>          viewport->inbound = false;
>>          viewport->base    = 0x0000000000000000ULL;
>>          viewport->target  = 0x0000000000000000ULL;
>> -        viewport->limit   = UINT32_MAX;
>> +        viewport->limit   = UINT64_MAX;
>>          viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
>>
>>          destination = &host->pci.memory;
>> @@ -558,7 +564,7 @@ static const VMStateDescription vmstate_designware_pcie_viewport = {
>>      .fields = (const VMStateField[]) {
>>          VMSTATE_UINT64(base, DesignwarePCIEViewport),
>>          VMSTATE_UINT64(target, DesignwarePCIEViewport),
>> -        VMSTATE_UINT32(limit, DesignwarePCIEViewport),
>> +        VMSTATE_UINT64(limit, DesignwarePCIEViewport),
>>          VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
>>          VMSTATE_END_OF_LIST()
>>      }
>> diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
>> index a35a3bd06c..6e06f54801 100644
>> --- a/include/hw/pci-host/designware.h
>> +++ b/include/hw/pci-host/designware.h
>> @@ -46,7 +46,7 @@ typedef struct DesignwarePCIEViewport {
>>
>>      uint64_t base;
>>      uint64_t target;
>> -    uint32_t limit;
>> +    uint64_t limit;
>>      uint32_t cr[2];
>>
>>      bool inbound;
Re: [PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost
Posted by Bernhard Beschow 4 months ago 

Am 17. Juli 2025 00:51:28 UTC schrieb zhangzhijie <zhangzhijie@bosc.ac.cn>:
>
>
>在 2025/7/17 1:53, Bernhard Beschow 写道:
>> 
>> 
>> Am 15. Juli 2025 06:44:00 UTC schrieb zhangzhijie <zhangzhijie@bosc.ac.cn>:
>>> 0. DW pcie support 64bit resource
>>> 1. DW version type using Linux kernel
>> 
>> Which machines in QEMU require this change?
>> 
>after support 64bit resource, will support on riscv

Nice. Is there a datasheet (standalone or for the riscv SoC using this IP block) which you could provide? The QEMU emulation has some bugs which I'd like to fix.

>>> 
>>> Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
>>> ---
>>> hw/pci-host/designware.c         | 12 +++++++++---
>>> include/hw/pci-host/designware.h |  2 +-
>>> 2 files changed, 10 insertions(+), 4 deletions(-)
>>> 
>>> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
>>> index f6e49ce9b8..99d791c0a7 100644
>>> --- a/hw/pci-host/designware.c
>>> +++ b/hw/pci-host/designware.c
>>> @@ -41,6 +41,8 @@
>>> #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
>>> #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
>>> #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
>>> +#define PCIE_VERSION_NUMBER                        0x8F8
>>> +#define PCIE_VERSION_TYPE                          0x8FC
>>> #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
>>> #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
>>> #define DESIGNWARE_PCIE_ATU_CR1                    0x904
>>> @@ -144,6 +146,10 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
>>>      uint32_t val;
>>> 
>>>      switch (address) {
>>> +    case PCIE_VERSION_NUMBER:
>>> +    case PCIE_VERSION_TYPE:
>>> +        val = 0x3534302a;
>>> +        break;
>>>      case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
>>>          /*
>>>           * Linux guest uses this register only to configure number of
>>> @@ -427,7 +433,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>>>          viewport->inbound = true;
>>>          viewport->base    = 0x0000000000000000ULL;
>>>          viewport->target  = 0x0000000000000000ULL;
>>> -        viewport->limit   = UINT32_MAX;
>>> +        viewport->limit   = UINT64_MAX;
>>>          viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
>>> 
>>>          source      = &host->pci.address_space_root;
>>> @@ -451,7 +457,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
>>>          viewport->inbound = false;
>>>          viewport->base    = 0x0000000000000000ULL;
>>>          viewport->target  = 0x0000000000000000ULL;
>>> -        viewport->limit   = UINT32_MAX;
>>> +        viewport->limit   = UINT64_MAX;
>>>          viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
>>> 
>>>          destination = &host->pci.memory;
>>> @@ -558,7 +564,7 @@ static const VMStateDescription vmstate_designware_pcie_viewport = {
>>>      .fields = (const VMStateField[]) {
>>>          VMSTATE_UINT64(base, DesignwarePCIEViewport),
>>>          VMSTATE_UINT64(target, DesignwarePCIEViewport),
>>> -        VMSTATE_UINT32(limit, DesignwarePCIEViewport),
>>> +        VMSTATE_UINT64(limit, DesignwarePCIEViewport),
>>>          VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
>>>          VMSTATE_END_OF_LIST()
>>>      }
>>> diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
>>> index a35a3bd06c..6e06f54801 100644
>>> --- a/include/hw/pci-host/designware.h
>>> +++ b/include/hw/pci-host/designware.h
>>> @@ -46,7 +46,7 @@ typedef struct DesignwarePCIEViewport {
>>> 
>>>      uint64_t base;
>>>      uint64_t target;
>>> -    uint32_t limit;
>>> +    uint64_t limit;
>>>      uint32_t cr[2];
>>> 
>>>      bool inbound;
>
Re: [PATCH v1] PCIE-Host Support 64Bit resource for DesignwarePCIEHost
Posted by zhangzhijie 4 months ago 
Hi

在 2025/7/17 18:24, Bernhard Beschow 写道:
> Nice. Is there a datasheet (standalone or for the riscv SoC using this IP block) which you could provide? The QEMU emulation has some bugs which I'd like to fix.


I not got designedware datasheet. I read Linux kernel code and found 
this feature. I think  dw rc support on every machine if you want.

Thanks.

Patchew 2.1-devel-b67e4c2

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