From: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20250704141927.38963-3-cohuck@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 2 --
target/arm/cpu-sysregs.h.inc | 2 ++
target/arm/helper.c | 4 ++--
target/arm/tcg/cpu64.c | 16 ++++++++--------
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 835700cfab8..008e5305782 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1082,8 +1082,6 @@ struct ArchCPU {
uint32_t reset_sctlr;
uint64_t pmceid0;
uint64_t pmceid1;
- uint64_t id_aa64afr0;
- uint64_t id_aa64afr1;
uint64_t clidr;
uint64_t mp_affinity; /* MP ID without feature bits */
/* The elements of this array are the CCSIDR values for each cache,
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index b96a3588043..44c877245ee 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -4,6 +4,8 @@ DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
+DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
+DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ae6231803e1..93da8f170ea 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7987,12 +7987,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->id_aa64afr0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64AFR0) },
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->id_aa64afr1 },
+ .resetvalue = GET_IDREG(isar, ID_AA64AFR1) },
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index e3183c53bb1..3a65d3903bf 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -428,8 +428,8 @@ static void aarch64_a64fx_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408),
SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000),
- cpu->id_aa64afr0 = 0x0000000000000000;
- cpu->id_aa64afr1 = 0x0000000000000000;
+ SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000);
+ SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100);
SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011);
@@ -676,8 +676,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0xb444c004; /* With DIC and IDC set */
cpu->dcz_blocksize = 4;
- cpu->id_aa64afr0 = 0x00000000;
- cpu->id_aa64afr1 = 0x00000000;
+ SET_IDREG(isar, ID_AA64AFR0, 0x00000000);
+ SET_IDREG(isar, ID_AA64AFR1, 0x00000000);
SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull),
SET_IDREG(isar, ID_AA64DFR1, 0x00000000),
SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
@@ -927,8 +927,8 @@ static void aarch64_a710_initfn(Object *obj)
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
SET_IDREG(isar, ID_AA64DFR1, 0);
- cpu->id_aa64afr0 = 0;
- cpu->id_aa64afr1 = 0;
+ SET_IDREG(isar, ID_AA64AFR0, 0);
+ SET_IDREG(isar, ID_AA64AFR1, 0);
SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull);
@@ -1029,8 +1029,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull);
SET_IDREG(isar, ID_AA64DFR1, 0);
- cpu->id_aa64afr0 = 0;
- cpu->id_aa64afr1 = 0;
+ SET_IDREG(isar, ID_AA64AFR0, 0);
+ SET_IDREG(isar, ID_AA64AFR1, 0);
SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull);
--
2.43.0