[v3] target/arm: Add FEAT_MEC to max cpu

[RFC PATCH-for-10.1 v3 0/5] target/arm: Add FEAT_MEC to max cpu

Gustavo Romero posted 5 patches 4 months, 1 week ago

Diff against v1 v2 v4 v5 v6 v7 v8 v9 v10
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250708191704.1068604-1-gustavo.romero@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

docs/system/arm/emulation.rst |   3 +
target/arm/cpu-features.h     |  15 +++
target/arm/cpu.h              |  29 +++++
target/arm/helper.c           | 208 ++++++++++++++++++++++++++++++++++
target/arm/internals.h        |  20 ++++
target/arm/tcg/cpu64.c        |   3 +
6 files changed, 278 insertions(+)

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[RFC PATCH-for-10.1 v3 0/5] target/arm: Add FEAT_MEC to max cpu

Posted by Gustavo Romero 4 months, 1 week ago

This series adds support for all FEAT_MEC registers to the arm64 max CPU.

It includes the FEAT_MEC registers but does not modify the translation regimes
to support the MECIDs. It also does not implement the two cache management yet.

I'm currently exploring possibilities to support FEAT_MEC encryption (or
obfuscation, for testing purposes) in QEMU for the various translation regimes
used on arm64.


Cheers,
Gustavo

Gustavo Romero (5):
  target/arm: Add the MECEn SCR_EL3 bit
  target/arm: Add FEAT_MEC registers
  target/arm: Add FEAT_SCTLR2
  target/arm: Add FEAT_TCR2
  target/arm: Advertise FEAT_MEC in cpu max

 docs/system/arm/emulation.rst |   3 +
 target/arm/cpu-features.h     |  15 +++
 target/arm/cpu.h              |  29 +++++
 target/arm/helper.c           | 208 ++++++++++++++++++++++++++++++++++
 target/arm/internals.h        |  20 ++++
 target/arm/tcg/cpu64.c        |   3 +
 6 files changed, 278 insertions(+)

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2.34.1