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[PATCH 1/5] arm/cpu: store id_afr0 into the idregs array

Cornelia Huck posted 5 patches 5 months, 2 weeks ago
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>
[PATCH 1/5] arm/cpu: store id_afr0 into the idregs array
Posted by Cornelia Huck 5 months, 2 weeks ago 
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
 hw/intc/armv7m_nvic.c        |  2 +-
 target/arm/cpu-sysregs.h.inc |  1 +
 target/arm/cpu.h             |  1 -
 target/arm/cpu64.c           |  4 ++--
 target/arm/helper.c          |  2 +-
 target/arm/tcg/cpu-v7m.c     | 12 ++++++------
 target/arm/tcg/cpu32.c       | 22 +++++++++++-----------
 target/arm/tcg/cpu64.c       | 16 ++++++++--------
 8 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6d85720f1b46..d93e593fcba8 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1279,7 +1279,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
             goto bad_offset;
         }
-        return cpu->id_afr0;
+        return GET_IDREG(isar, ID_AFR0);
     case 0xd50: /* MMFR0.  */
         if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
             goto bad_offset;
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index cb99286f7048..b96a35880430 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -14,6 +14,7 @@ DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
 DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
 DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
 DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
+DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)
 DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
 DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
 DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 033815392385..ca8ad1cc27a8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1066,7 +1066,6 @@ struct ArchCPU {
     uint32_t reset_sctlr;
     uint64_t pmceid0;
     uint64_t pmceid1;
-    uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
     uint64_t clidr;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1f3406708bd7..28b8f7db949d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -655,7 +655,7 @@ static void aarch64_a57_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x03010066);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10101105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
@@ -717,7 +717,7 @@ static void aarch64_a53_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x03010066);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10101105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c311d2df2170..2f57ab4d87da 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7805,7 +7805,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
-              .resetvalue = cpu->id_afr0 },
+              .resetvalue = GET_IDREG(isar, ID_AFR0)},
             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index eddd7117d5bb..a65b83fe9905 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000030);
     SET_IDREG(isar, ID_PFR1, 0x00000200);
     SET_IDREG(isar, ID_DFR0, 0x00100000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00000030);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x00000000);
@@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000030);
     SET_IDREG(isar, ID_PFR1, 0x00000200);
     SET_IDREG(isar, ID_DFR0, 0x00100000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00000030);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x00000000);
@@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000030);
     SET_IDREG(isar, ID_PFR1, 0x00000200);
     SET_IDREG(isar, ID_DFR0, 0x00100000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00000030);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x00000000);
@@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000030);
     SET_IDREG(isar, ID_PFR1, 0x00000200);
     SET_IDREG(isar, ID_DFR0, 0x00100000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00100030);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x01000000);
@@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000030);
     SET_IDREG(isar, ID_PFR1, 0x00000210);
     SET_IDREG(isar, ID_DFR0, 0x00200000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00101F40);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x01000000);
@@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x20000030);
     SET_IDREG(isar, ID_PFR1, 0x00000230);
     SET_IDREG(isar, ID_DFR0, 0x10200000);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00111040);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x01000000);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 942b636aa5bd..03cbe42f22f8 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -225,7 +225,7 @@ static void arm1136_r2_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x111);
     SET_IDREG(isar, ID_PFR1, 0x1);
     SET_IDREG(isar, ID_DFR0, 0x2);
-    cpu->id_afr0 = 0x3;
+    SET_IDREG(isar, ID_AFR0, 0x3);
     SET_IDREG(isar, ID_MMFR0, 0x01130003);
     SET_IDREG(isar, ID_MMFR1, 0x10030302);
     SET_IDREG(isar, ID_MMFR2, 0x01222110);
@@ -257,7 +257,7 @@ static void arm1136_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x111);
     SET_IDREG(isar, ID_PFR1, 0x1);
     SET_IDREG(isar, ID_DFR0, 0x2);
-    cpu->id_afr0 = 0x3;
+    SET_IDREG(isar, ID_AFR0, 0x3);
     SET_IDREG(isar, ID_MMFR0, 0x01130003);
     SET_IDREG(isar, ID_MMFR1, 0x10030302);
     SET_IDREG(isar, ID_MMFR2, 0x01222110);
@@ -290,7 +290,7 @@ static void arm1176_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x111);
     SET_IDREG(isar, ID_PFR1, 0x11);
     SET_IDREG(isar, ID_DFR0, 0x33);
-    cpu->id_afr0 = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x01130003);
     SET_IDREG(isar, ID_MMFR1, 0x10030302);
     SET_IDREG(isar, ID_MMFR2, 0x01222100);
@@ -320,7 +320,7 @@ static void arm11mpcore_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x111);
     SET_IDREG(isar, ID_PFR1, 0x1);
     SET_IDREG(isar, ID_DFR0, 0);
-    cpu->id_afr0 = 0x2;
+    SET_IDREG(isar, ID_AFR0, 0x2);
     SET_IDREG(isar, ID_MMFR0, 0x01100103);
     SET_IDREG(isar, ID_MMFR1, 0x10020302);
     SET_IDREG(isar, ID_MMFR2, 0x01222000);
@@ -360,7 +360,7 @@ static void cortex_a8_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x1031);
     SET_IDREG(isar, ID_PFR1, 0x11);
     SET_IDREG(isar, ID_DFR0, 0x400);
-    cpu->id_afr0 = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x31100003);
     SET_IDREG(isar, ID_MMFR1, 0x20000000);
     SET_IDREG(isar, ID_MMFR2, 0x01202000);
@@ -436,7 +436,7 @@ static void cortex_a9_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x1031);
     SET_IDREG(isar, ID_PFR1, 0x11);
     SET_IDREG(isar, ID_DFR0, 0x000);
-    cpu->id_afr0 = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x00100103);
     SET_IDREG(isar, ID_MMFR1, 0x20000000);
     SET_IDREG(isar, ID_MMFR2, 0x01230000);
@@ -502,7 +502,7 @@ static void cortex_a7_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00001131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x02010555);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10101105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01240000);
@@ -554,7 +554,7 @@ static void cortex_a15_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00001131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x02010555);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10201105);
     SET_IDREG(isar, ID_MMFR1, 0x20000000);
     SET_IDREG(isar, ID_MMFR2, 0x01240000);
@@ -598,7 +598,7 @@ static void cortex_r5_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x0131);
     SET_IDREG(isar, ID_PFR1, 0x001);
     SET_IDREG(isar, ID_DFR0, 0x010400);
-    cpu->id_afr0 = 0x0;
+    SET_IDREG(isar, ID_AFR0, 0x0);
     SET_IDREG(isar, ID_MMFR0, 0x0210030);
     SET_IDREG(isar, ID_MMFR1, 0x00000000);
     SET_IDREG(isar, ID_MMFR2, 0x01200000);
@@ -745,7 +745,7 @@ static void cortex_r52_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x10111001);
     SET_IDREG(isar, ID_DFR0, 0x03010006);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x00211040);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01200000);
@@ -977,7 +977,7 @@ static void arm_max_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x03010066);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10101105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 937f29e253d7..3f4fb003f440 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -52,7 +52,7 @@ static void aarch64_a35_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x03010066);
-    cpu->id_afr0 = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x10201105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
@@ -227,7 +227,7 @@ static void aarch64_a55_initfn(Object *obj)
     SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
     SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
     SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
-    cpu->id_afr0       = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_DFR0, 0x04010088);
     SET_IDREG(isar, ID_ISAR0, 0x02101110);
     SET_IDREG(isar, ID_ISAR1, 0x13112111);
@@ -298,7 +298,7 @@ static void aarch64_a72_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x00000131);
     SET_IDREG(isar, ID_PFR1, 0x00011011);
     SET_IDREG(isar, ID_DFR0, 0x03010066);
-    cpu->id_afr0 = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_MMFR0, 0x10201105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
@@ -360,7 +360,7 @@ static void aarch64_a76_initfn(Object *obj)
     SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
     SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
     SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
-    cpu->id_afr0       = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_DFR0, 0x04010088);
     SET_IDREG(isar, ID_ISAR0, 0x02101110);
     SET_IDREG(isar, ID_ISAR1, 0x13112111);
@@ -608,7 +608,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
     SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
     SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
     SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
-    cpu->id_afr0       = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_DFR0, 0x04010088);
     SET_IDREG(isar, ID_ISAR0, 0x02101110);
     SET_IDREG(isar, ID_ISAR1, 0x13112111);
@@ -687,7 +687,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
     SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull),
     SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
     SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
-    cpu->id_afr0       = 0x00000000;
+    SET_IDREG(isar, ID_AFR0, 0x00000000);
     SET_IDREG(isar, ID_DFR0, 0x15011099);
     SET_IDREG(isar, ID_ISAR0, 0x02101110);
     SET_IDREG(isar, ID_ISAR1, 0x13112111);
@@ -905,7 +905,7 @@ static void aarch64_a710_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x21110131);
     SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
     SET_IDREG(isar, ID_DFR0, 0x16011099);
-    cpu->id_afr0       = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x10201105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
@@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
     SET_IDREG(isar, ID_PFR0, 0x21110131);
     SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
     SET_IDREG(isar, ID_DFR0, 0x16011099);
-    cpu->id_afr0       = 0;
+    SET_IDREG(isar, ID_AFR0, 0);
     SET_IDREG(isar, ID_MMFR0, 0x10201105);
     SET_IDREG(isar, ID_MMFR1, 0x40000000);
     SET_IDREG(isar, ID_MMFR2, 0x01260000);
-- 
2.50.0
Re: [PATCH 1/5] arm/cpu: store id_afr0 into the idregs array
Posted by Eric Auger 5 months, 1 week ago 
Hi Connie,

On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  hw/intc/armv7m_nvic.c        |  2 +-
>  target/arm/cpu-sysregs.h.inc |  1 +
>  target/arm/cpu.h             |  1 -
>  target/arm/cpu64.c           |  4 ++--
>  target/arm/helper.c          |  2 +-
>  target/arm/tcg/cpu-v7m.c     | 12 ++++++------
>  target/arm/tcg/cpu32.c       | 22 +++++++++++-----------
>  target/arm/tcg/cpu64.c       | 16 ++++++++--------
>  8 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 6d85720f1b46..d93e593fcba8 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -1279,7 +1279,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
>          if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
>              goto bad_offset;
>          }
> -        return cpu->id_afr0;
> +        return GET_IDREG(isar, ID_AFR0);
>      case 0xd50: /* MMFR0.  */
>          if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
>              goto bad_offset;
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index cb99286f7048..b96a35880430 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
>  DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
>  DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
>  DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
> +DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)
>  DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
>  DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
>  DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 033815392385..ca8ad1cc27a8 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1066,7 +1066,6 @@ struct ArchCPU {
>      uint32_t reset_sctlr;
>      uint64_t pmceid0;
>      uint64_t pmceid1;
> -    uint32_t id_afr0;
>      uint64_t id_aa64afr0;
>      uint64_t id_aa64afr1;
>      uint64_t clidr;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 1f3406708bd7..28b8f7db949d 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -655,7 +655,7 @@ static void aarch64_a57_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10101105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> @@ -717,7 +717,7 @@ static void aarch64_a53_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10101105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c311d2df2170..2f57ab4d87da 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7805,7 +7805,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
>                .access = PL1_R, .type = ARM_CP_CONST,
>                .accessfn = access_aa32_tid3,
> -              .resetvalue = cpu->id_afr0 },
> +              .resetvalue = GET_IDREG(isar, ID_AFR0)},
>              { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
>                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
>                .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
> index eddd7117d5bb..a65b83fe9905 100644
> --- a/target/arm/tcg/cpu-v7m.c
> +++ b/target/arm/tcg/cpu-v7m.c
> @@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000200);
>      SET_IDREG(isar, ID_DFR0, 0x00100000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00000030);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x00000000);
> @@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000200);
>      SET_IDREG(isar, ID_DFR0, 0x00100000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00000030);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x00000000);
> @@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000200);
>      SET_IDREG(isar, ID_DFR0, 0x00100000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00000030);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x00000000);
> @@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000200);
>      SET_IDREG(isar, ID_DFR0, 0x00100000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00100030);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01000000);
> @@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000210);
>      SET_IDREG(isar, ID_DFR0, 0x00200000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00101F40);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01000000);
> @@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x20000030);
>      SET_IDREG(isar, ID_PFR1, 0x00000230);
>      SET_IDREG(isar, ID_DFR0, 0x10200000);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00111040);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01000000);
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 942b636aa5bd..03cbe42f22f8 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -225,7 +225,7 @@ static void arm1136_r2_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x111);
>      SET_IDREG(isar, ID_PFR1, 0x1);
>      SET_IDREG(isar, ID_DFR0, 0x2);
> -    cpu->id_afr0 = 0x3;
> +    SET_IDREG(isar, ID_AFR0, 0x3);
>      SET_IDREG(isar, ID_MMFR0, 0x01130003);
>      SET_IDREG(isar, ID_MMFR1, 0x10030302);
>      SET_IDREG(isar, ID_MMFR2, 0x01222110);
> @@ -257,7 +257,7 @@ static void arm1136_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x111);
>      SET_IDREG(isar, ID_PFR1, 0x1);
>      SET_IDREG(isar, ID_DFR0, 0x2);
> -    cpu->id_afr0 = 0x3;
> +    SET_IDREG(isar, ID_AFR0, 0x3);
>      SET_IDREG(isar, ID_MMFR0, 0x01130003);
>      SET_IDREG(isar, ID_MMFR1, 0x10030302);
>      SET_IDREG(isar, ID_MMFR2, 0x01222110);
> @@ -290,7 +290,7 @@ static void arm1176_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x111);
>      SET_IDREG(isar, ID_PFR1, 0x11);
>      SET_IDREG(isar, ID_DFR0, 0x33);
> -    cpu->id_afr0 = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x01130003);
>      SET_IDREG(isar, ID_MMFR1, 0x10030302);
>      SET_IDREG(isar, ID_MMFR2, 0x01222100);
> @@ -320,7 +320,7 @@ static void arm11mpcore_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x111);
>      SET_IDREG(isar, ID_PFR1, 0x1);
>      SET_IDREG(isar, ID_DFR0, 0);
> -    cpu->id_afr0 = 0x2;
> +    SET_IDREG(isar, ID_AFR0, 0x2);
>      SET_IDREG(isar, ID_MMFR0, 0x01100103);
>      SET_IDREG(isar, ID_MMFR1, 0x10020302);
>      SET_IDREG(isar, ID_MMFR2, 0x01222000);
> @@ -360,7 +360,7 @@ static void cortex_a8_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x1031);
>      SET_IDREG(isar, ID_PFR1, 0x11);
>      SET_IDREG(isar, ID_DFR0, 0x400);
> -    cpu->id_afr0 = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x31100003);
>      SET_IDREG(isar, ID_MMFR1, 0x20000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01202000);
> @@ -436,7 +436,7 @@ static void cortex_a9_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x1031);
>      SET_IDREG(isar, ID_PFR1, 0x11);
>      SET_IDREG(isar, ID_DFR0, 0x000);
> -    cpu->id_afr0 = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x00100103);
>      SET_IDREG(isar, ID_MMFR1, 0x20000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01230000);
> @@ -502,7 +502,7 @@ static void cortex_a7_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00001131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x02010555);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10101105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01240000);
> @@ -554,7 +554,7 @@ static void cortex_a15_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00001131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x02010555);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10201105);
>      SET_IDREG(isar, ID_MMFR1, 0x20000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01240000);
> @@ -598,7 +598,7 @@ static void cortex_r5_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x0131);
>      SET_IDREG(isar, ID_PFR1, 0x001);
>      SET_IDREG(isar, ID_DFR0, 0x010400);
> -    cpu->id_afr0 = 0x0;
> +    SET_IDREG(isar, ID_AFR0, 0x0);
>      SET_IDREG(isar, ID_MMFR0, 0x0210030);
>      SET_IDREG(isar, ID_MMFR1, 0x00000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01200000);
> @@ -745,7 +745,7 @@ static void cortex_r52_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x10111001);
>      SET_IDREG(isar, ID_DFR0, 0x03010006);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x00211040);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01200000);
> @@ -977,7 +977,7 @@ static void arm_max_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10101105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 937f29e253d7..3f4fb003f440 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -52,7 +52,7 @@ static void aarch64_a35_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    cpu->id_afr0 = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x10201105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> @@ -227,7 +227,7 @@ static void aarch64_a55_initfn(Object *obj)
>      SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
>      SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
>      SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> -    cpu->id_afr0       = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_DFR0, 0x04010088);
>      SET_IDREG(isar, ID_ISAR0, 0x02101110);
>      SET_IDREG(isar, ID_ISAR1, 0x13112111);
> @@ -298,7 +298,7 @@ static void aarch64_a72_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x00000131);
>      SET_IDREG(isar, ID_PFR1, 0x00011011);
>      SET_IDREG(isar, ID_DFR0, 0x03010066);
> -    cpu->id_afr0 = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_MMFR0, 0x10201105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> @@ -360,7 +360,7 @@ static void aarch64_a76_initfn(Object *obj)
>      SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
>      SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
>      SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> -    cpu->id_afr0       = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_DFR0, 0x04010088);
>      SET_IDREG(isar, ID_ISAR0, 0x02101110);
>      SET_IDREG(isar, ID_ISAR1, 0x13112111);
> @@ -608,7 +608,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
>      SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
>      SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
>      SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> -    cpu->id_afr0       = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_DFR0, 0x04010088);
>      SET_IDREG(isar, ID_ISAR0, 0x02101110);
>      SET_IDREG(isar, ID_ISAR1, 0x13112111);
> @@ -687,7 +687,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
>      SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull),
>      SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
>      SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> -    cpu->id_afr0       = 0x00000000;
> +    SET_IDREG(isar, ID_AFR0, 0x00000000);
>      SET_IDREG(isar, ID_DFR0, 0x15011099);
>      SET_IDREG(isar, ID_ISAR0, 0x02101110);
>      SET_IDREG(isar, ID_ISAR1, 0x13112111);
> @@ -905,7 +905,7 @@ static void aarch64_a710_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x21110131);
>      SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
>      SET_IDREG(isar, ID_DFR0, 0x16011099);
> -    cpu->id_afr0       = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x10201105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
> @@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
>      SET_IDREG(isar, ID_PFR0, 0x21110131);
>      SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
>      SET_IDREG(isar, ID_DFR0, 0x16011099);
> -    cpu->id_afr0       = 0;
> +    SET_IDREG(isar, ID_AFR0, 0);
>      SET_IDREG(isar, ID_MMFR0, 0x10201105);
>      SET_IDREG(isar, ID_MMFR1, 0x40000000);
>      SET_IDREG(isar, ID_MMFR2, 0x01260000);
Re: [PATCH 1/5] arm/cpu: store id_afr0 into the idregs array
Posted by Philippe Mathieu-Daudé 5 months, 2 weeks ago 
On 4/7/25 16:19, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
>   hw/intc/armv7m_nvic.c        |  2 +-
>   target/arm/cpu-sysregs.h.inc |  1 +
>   target/arm/cpu.h             |  1 -
>   target/arm/cpu64.c           |  4 ++--
>   target/arm/helper.c          |  2 +-
>   target/arm/tcg/cpu-v7m.c     | 12 ++++++------
>   target/arm/tcg/cpu32.c       | 22 +++++++++++-----------
>   target/arm/tcg/cpu64.c       | 16 ++++++++--------
>   8 files changed, 30 insertions(+), 30 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Patchew 2.1-devel-b67e4c2

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