target/riscv: Fix MEPC/SEPC bit masking

[PATCH 0/2] target/riscv: Fix MEPC/SEPC bit masking

Charalampos Mitrodimas posted 2 patches 5 months, 2 weeks ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250703182157.281320-1-charmitro@posteo.net

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/csr.c                        |  8 +--
target/riscv/internals.h                  | 11 ++++
target/riscv/op_helper.c                  |  4 +-
tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
tests/tcg/riscv64/test-mepc-masking.S     | 73 +++++++++++++++++++++++
5 files changed, 94 insertions(+), 6 deletions(-)
create mode 100644 tests/tcg/riscv64/test-mepc-masking.S

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[PATCH 0/2] target/riscv: Fix MEPC/SEPC bit masking

Posted by Charalampos Mitrodimas 5 months, 2 weeks ago

This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the
lower bits were not properly masked according to the RISC-V specification.

The issue was discovered when vectored mode bits from STVEC were
written to MEPC and not properly cleared, causing incorrect behavior
on MRET.

Charalampos Mitrodimas (2):
  target/riscv: Fix MEPC/SEPC bit masking for IALIGN
  tests/tcg/riscv64: Add test for MEPC bit masking

 target/riscv/csr.c                        |  8 +--
 target/riscv/internals.h                  | 11 ++++
 target/riscv/op_helper.c                  |  4 +-
 tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
 tests/tcg/riscv64/test-mepc-masking.S     | 73 +++++++++++++++++++++++
 5 files changed, 94 insertions(+), 6 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-mepc-masking.S

-- 
2.47.2

Re: [PATCH 0/2] target/riscv: Fix MEPC/SEPC bit masking

Posted by Alistair Francis 5 months, 2 weeks ago

On Fri, Jul 4, 2025 at 4:24 AM Charalampos Mitrodimas
<charmitro@posteo.net> wrote:
>
> This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the
> lower bits were not properly masked according to the RISC-V specification.
>
> The issue was discovered when vectored mode bits from STVEC were
> written to MEPC and not properly cleared, causing incorrect behavior
> on MRET.
>
> Charalampos Mitrodimas (2):
>   target/riscv: Fix MEPC/SEPC bit masking for IALIGN
>   tests/tcg/riscv64: Add test for MEPC bit masking

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/csr.c                        |  8 +--
>  target/riscv/internals.h                  | 11 ++++
>  target/riscv/op_helper.c                  |  4 +-
>  tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
>  tests/tcg/riscv64/test-mepc-masking.S     | 73 +++++++++++++++++++++++
>  5 files changed, 94 insertions(+), 6 deletions(-)
>  create mode 100644 tests/tcg/riscv64/test-mepc-masking.S
>
> --
> 2.47.2
>
>