On 7/2/25 05:19, William Kosasih wrote:
> This patch adds alignment checks in the store operations (when stacking the
> return pc and psr) in the BLXNS instruction.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154
> Signed-off-by: William Kosasih <kosasihwilliam4@gmail.com>
> ---
> target/arm/tcg/m_helper.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
> index 251e12edf9..f342d93489 100644
> --- a/target/arm/tcg/m_helper.c
> +++ b/target/arm/tcg/m_helper.c
> @@ -632,8 +632,11 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
> }
>
> /* Note that these stores can throw exceptions on MPU faults */
> - cpu_stl_data_ra(env, sp, nextinst, GETPC());
> - cpu_stl_data_ra(env, sp + 4, saved_psr, GETPC());
> + ARMMMUIdx mmu_idx = arm_mmu_idx(env);
> + MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN,
> + arm_to_core_mmu_idx(mmu_idx));
> + cpu_stl_mmu(env, sp, nextinst, oi, GETPC());
> + cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC());
>
> env->regs[13] = sp;
> env->regs[14] = 0xfeffffff;
I'm somewhat surprised the spec says sp % 8 is unpredictable rather than forcing an
alignment fault. But anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~