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[PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts

Jay Chang posted 2 patches 4 months, 2 weeks ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
[PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts
Posted by Jay Chang 4 months, 2 weeks ago 
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smaia except
excluding the machine-level CSRs and behavior not directly visible to
supervisor level."

Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
aia_smode32 predicate.

Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jay Chang <jay.chang@sifive.com>
---
 target/riscv/csr.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0e0ad37654..74ec0e1c60 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -374,8 +374,11 @@ static RISCVException aia_smode(CPURISCVState *env, int csrno)
 static RISCVException aia_smode32(CPURISCVState *env, int csrno)
 {
     int ret;
+    int csr_priv = get_field(csrno, 0x300);
 
-    if (!riscv_cpu_cfg(env)->ext_ssaia) {
+    if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    } else if (!riscv_cpu_cfg(env)->ext_ssaia) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -5911,7 +5914,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MVIP]     = { "mvip",     aia_any, NULL, NULL, rmw_mvip    },
 
     /* Machine-Level High-Half CSRs (AIA) */
-    [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
+    [CSR_MIDELEGH] = { "midelegh", aia_smode32, NULL, NULL, rmw_midelegh },
     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
     [CSR_MVIENH]   = { "mvienh",   aia_any32, NULL, NULL, rmw_mvienh   },
     [CSR_MVIPH]    = { "mviph",    aia_any32, NULL, NULL, rmw_mviph    },
-- 
2.48.1
Re: [PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts
Posted by Nutty Liu 4 months, 2 weeks ago 
On 7/1/2025 11:00 AM, Jay Chang wrote:
> RISC-V AIA Spec states:
> "For a machine-level environment, extension Smaia encompasses all added
> CSRs and all modifications to interrupt response behavior that the AIA
> specifies for a hart, over all privilege levels. For a supervisor-level
> environment, extension Ssaia is essentially the same as Smaia except
> excluding the machine-level CSRs and behavior not directly visible to
> supervisor level."
>
> Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
> aia_smode32 predicate.
>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Jay Chang <jay.chang@sifive.com>
> ---
>   target/riscv/csr.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0e0ad37654..74ec0e1c60 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -374,8 +374,11 @@ static RISCVException aia_smode(CPURISCVState *env, int csrno)
>   static RISCVException aia_smode32(CPURISCVState *env, int csrno)
>   {
>       int ret;
> +    int csr_priv = get_field(csrno, 0x300);
>   
> -    if (!riscv_cpu_cfg(env)->ext_ssaia) {
> +    if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    } else if (!riscv_cpu_cfg(env)->ext_ssaia) {

+    if ((csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) ||
+        (!riscv_cpu_cfg(env)->ext_ssaia)) {

Would the above code be better ?
Otherwise,
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>

Thanks,
Nutty

>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -5911,7 +5914,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>       [CSR_MVIP]     = { "mvip",     aia_any, NULL, NULL, rmw_mvip    },
>   
>       /* Machine-Level High-Half CSRs (AIA) */
> -    [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
> +    [CSR_MIDELEGH] = { "midelegh", aia_smode32, NULL, NULL, rmw_midelegh },
>       [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
>       [CSR_MVIENH]   = { "mvienh",   aia_any32, NULL, NULL, rmw_mvienh   },
>       [CSR_MVIPH]    = { "mviph",    aia_any32, NULL, NULL, rmw_mviph    },
Re: [PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts
Posted by Jay Chang 4 months, 1 week ago 
I intended to separate the S-mode and M-mode handling.
Do you think this change could improve performance?

Thanks,
Jay Chang

On Tue, Jul 1, 2025 at 11:46 AM Nutty Liu <liujingqi@lanxincomputing.com>
wrote:

> On 7/1/2025 11:00 AM, Jay Chang wrote:
> > RISC-V AIA Spec states:
> > "For a machine-level environment, extension Smaia encompasses all added
> > CSRs and all modifications to interrupt response behavior that the AIA
> > specifies for a hart, over all privilege levels. For a supervisor-level
> > environment, extension Ssaia is essentially the same as Smaia except
> > excluding the machine-level CSRs and behavior not directly visible to
> > supervisor level."
> >
> > Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
> > aia_smode32 predicate.
> >
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Signed-off-by: Jay Chang <jay.chang@sifive.com>
> > ---
> >   target/riscv/csr.c | 7 +++++--
> >   1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 0e0ad37654..74ec0e1c60 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -374,8 +374,11 @@ static RISCVException aia_smode(CPURISCVState *env,
> int csrno)
> >   static RISCVException aia_smode32(CPURISCVState *env, int csrno)
> >   {
> >       int ret;
> > +    int csr_priv = get_field(csrno, 0x300);
> >
> > -    if (!riscv_cpu_cfg(env)->ext_ssaia) {
> > +    if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
> > +        return RISCV_EXCP_ILLEGAL_INST;
> > +    } else if (!riscv_cpu_cfg(env)->ext_ssaia) {
>
> +    if ((csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) ||
> +        (!riscv_cpu_cfg(env)->ext_ssaia)) {
>
> Would the above code be better ?
> Otherwise,
> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
>
> Thanks,
> Nutty
>
> >           return RISCV_EXCP_ILLEGAL_INST;
> >       }
> >
> > @@ -5911,7 +5914,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >       [CSR_MVIP]     = { "mvip",     aia_any, NULL, NULL, rmw_mvip    },
> >
> >       /* Machine-Level High-Half CSRs (AIA) */
> > -    [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh
> },
> > +    [CSR_MIDELEGH] = { "midelegh", aia_smode32, NULL, NULL,
> rmw_midelegh },
> >       [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh
>  },
> >       [CSR_MVIENH]   = { "mvienh",   aia_any32, NULL, NULL, rmw_mvienh
>  },
> >       [CSR_MVIPH]    = { "mviph",    aia_any32, NULL, NULL, rmw_mviph
> },
>

Patchew 2.1-devel-b67e4c2

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