From: Kane-Chen-AS <kane_chen@aspeedtech.com>

This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.

If no external block backend is provided via the "drive" property, the
model automatically allocates an internal RAM-backed storage buffer
to hold OTP data, enabling simplified usage without CLI configuration.

Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
---
 include/hw/nvram/aspeed_otp.h |  33 ++++++++++
 hw/nvram/aspeed_otp.c         | 113 ++++++++++++++++++++++++++++++++++
 hw/nvram/meson.build          |   4 ++
 3 files changed, 150 insertions(+)
 create mode 100644 include/hw/nvram/aspeed_otp.h
 create mode 100644 hw/nvram/aspeed_otp.c

diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h
new file mode 100644
index 0000000000..22b2195a00
--- /dev/null
+++ b/include/hw/nvram/aspeed_otp.h
@@ -0,0 +1,33 @@
+/*
+ *  ASPEED OTP (One-Time Programmable) memory
+ *
+ *  Copyright (C) 2025 Aspeed
+ *
+ *  SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef ASPEED_OTP_H
+#define ASPEED_OTP_H
+
+#include "system/memory.h"
+#include "hw/block/block.h"
+#include "system/address-spaces.h"
+
+#define TYPE_ASPEED_OTP "aspeed.otp"
+OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
+
+typedef struct AspeedOTPState {
+    DeviceState parent_obj;
+
+    BlockBackend *blk;
+
+    uint64_t size;
+
+    AddressSpace as;
+
+    MemoryRegion mmio;
+
+    uint8_t *storage;
+} AspeedOTPState;
+
+#endif /* ASPEED_OTP_H */
diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
new file mode 100644
index 0000000000..f018c58713
--- /dev/null
+++ b/hw/nvram/aspeed_otp.c
@@ -0,0 +1,113 @@
+/*
+ *  ASPEED OTP (One-Time Programmable) memory
+ *
+ *  Copyright (C) 2025 Aspeed
+ *
+ *  SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "system/block-backend-global-state.h"
+#include "system/block-backend-io.h"
+#include "hw/qdev-properties.h"
+#include "hw/nvram/aspeed_otp.h"
+
+static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
+{
+    AspeedOTPState *s = opaque;
+    uint64_t val = 0;
+
+    memcpy(&val, s->storage + offset, size);
+
+    return val;
+}
+
+static void aspeed_otp_write(void *opaque, hwaddr offset,
+                                uint64_t val, unsigned size)
+{
+    AspeedOTPState *s = opaque;
+
+    memcpy(s->storage + offset, &val, size);
+}
+
+static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
+{
+    uint32_t *p;
+    int i, num;
+    uint64_t perm;
+
+    if (s->blk) {
+        perm = BLK_PERM_CONSISTENT_READ |
+               (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
+        if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
+            return false;
+        }
+        if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
+            error_setg(errp, "Failed to read the initial flash content");
+            return false;
+        }
+    } else {
+        num = s->size / sizeof(uint32_t);
+        p = (uint32_t *)s->storage;
+        for (i = 0; i < num; i++) {
+            p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
+        }
+    }
+    return true;
+}
+
+static const MemoryRegionOps aspeed_otp_ops = {
+    .read = aspeed_otp_read,
+    .write = aspeed_otp_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
+};
+
+static void aspeed_otp_realize(DeviceState *dev, Error **errp)
+{
+    AspeedOTPState *s = ASPEED_OTP(dev);
+
+    if (s->size == 0) {
+        error_setg(errp, "aspeed.otp: 'size' property must be set");
+        return;
+    }
+
+    s->storage = blk_blockalign(s->blk, s->size);
+
+    if (!aspeed_otp_init_storage(s, errp)) {
+        return;
+    }
+
+    memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
+                          s, "aspeed.otp", s->size);
+    address_space_init(&s->as, &s->mmio, NULL);
+}
+
+static const Property aspeed_otp_properties[] = {
+    DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
+    DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk),
+};
+
+static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    dc->realize = aspeed_otp_realize;
+    device_class_set_props(dc, aspeed_otp_properties);
+}
+
+static const TypeInfo aspeed_otp_info = {
+    .name          = TYPE_ASPEED_OTP,
+    .parent        = TYPE_DEVICE,
+    .instance_size = sizeof(AspeedOTPState),
+    .class_init    = aspeed_otp_class_init,
+};
+
+static void aspeed_otp_register_types(void)
+{
+    type_register_static(&aspeed_otp_info);
+}
+
+type_init(aspeed_otp_register_types)
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 10f3639db6..b66f23605b 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
 
 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
 specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
+
+system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+  'aspeed_otp.c',
+  ))
\ No newline at end of file
-- 
2.43.0

On 6/30/25 07:17, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> 
> This patch introduces a QEMU model of the ASPEED One-Time Programmable
> (OTP) memory, used for secure fuse storage. The model simulates a
> word-addressable OTP region with a memory-like interface via a dedicated
> AddressSpace.
> 
> If no external block backend is provided via the "drive" property, the
> model automatically allocates an internal RAM-backed storage buffer
> to hold OTP data, enabling simplified usage without CLI configuration.
> 
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
>   include/hw/nvram/aspeed_otp.h |  33 ++++++++++
>   hw/nvram/aspeed_otp.c         | 113 ++++++++++++++++++++++++++++++++++
>   hw/nvram/meson.build          |   4 ++
>   3 files changed, 150 insertions(+)
>   create mode 100644 include/hw/nvram/aspeed_otp.h
>   create mode 100644 hw/nvram/aspeed_otp.c
> 
> diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h
> new file mode 100644
> index 0000000000..22b2195a00
> --- /dev/null
> +++ b/include/hw/nvram/aspeed_otp.h
> @@ -0,0 +1,33 @@
> +/*
> + *  ASPEED OTP (One-Time Programmable) memory
> + *
> + *  Copyright (C) 2025 Aspeed
> + *
> + *  SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef ASPEED_OTP_H
> +#define ASPEED_OTP_H
> +
> +#include "system/memory.h"
> +#include "hw/block/block.h"
> +#include "system/address-spaces.h"
> +
> +#define TYPE_ASPEED_OTP "aspeed.otp"

Please change to "aspeed-otp" so that we can use :

	-global aspeed-otp.drive="foo"

to define a backend.


Thanks,

C.



> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
> +
> +typedef struct AspeedOTPState {
> +    DeviceState parent_obj;
> +
> +    BlockBackend *blk;
> +
> +    uint64_t size;
> +
> +    AddressSpace as;
> +
> +    MemoryRegion mmio;
> +
> +    uint8_t *storage;
> +} AspeedOTPState;
> +
> +#endif /* ASPEED_OTP_H */
> diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
> new file mode 100644
> index 0000000000..f018c58713
> --- /dev/null
> +++ b/hw/nvram/aspeed_otp.c
> @@ -0,0 +1,113 @@
> +/*
> + *  ASPEED OTP (One-Time Programmable) memory
> + *
> + *  Copyright (C) 2025 Aspeed
> + *
> + *  SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "system/block-backend-global-state.h"
> +#include "system/block-backend-io.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/nvram/aspeed_otp.h"
> +
> +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +    AspeedOTPState *s = opaque;
> +    uint64_t val = 0;
> +
> +    memcpy(&val, s->storage + offset, size);
> +
> +    return val;
> +}
> +
> +static void aspeed_otp_write(void *opaque, hwaddr offset,
> +                                uint64_t val, unsigned size)
> +{
> +    AspeedOTPState *s = opaque;
> +
> +    memcpy(s->storage + offset, &val, size);
> +}
> +
> +static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
> +{
> +    uint32_t *p;
> +    int i, num;
> +    uint64_t perm;
> +
> +    if (s->blk) {
> +        perm = BLK_PERM_CONSISTENT_READ |
> +               (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
> +        if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
> +            return false;
> +        }
> +        if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
> +            error_setg(errp, "Failed to read the initial flash content");
> +            return false;
> +        }
> +    } else {
> +        num = s->size / sizeof(uint32_t);
> +        p = (uint32_t *)s->storage;
> +        for (i = 0; i < num; i++) {
> +            p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
> +        }
> +    }
> +    return true;
> +}
> +
> +static const MemoryRegionOps aspeed_otp_ops = {
> +    .read = aspeed_otp_read,
> +    .write = aspeed_otp_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .valid.min_access_size = 1,
> +    .valid.max_access_size = 4,
> +};
> +
> +static void aspeed_otp_realize(DeviceState *dev, Error **errp)
> +{
> +    AspeedOTPState *s = ASPEED_OTP(dev);
> +
> +    if (s->size == 0) {
> +        error_setg(errp, "aspeed.otp: 'size' property must be set");
> +        return;
> +    }
> +
> +    s->storage = blk_blockalign(s->blk, s->size);
> +
> +    if (!aspeed_otp_init_storage(s, errp)) {
> +        return;
> +    }
> +
> +    memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
> +                          s, "aspeed.otp", s->size);
> +    address_space_init(&s->as, &s->mmio, NULL);
> +}
> +
> +static const Property aspeed_otp_properties[] = {
> +    DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
> +    DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk),
> +};
> +
> +static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    dc->realize = aspeed_otp_realize;
> +    device_class_set_props(dc, aspeed_otp_properties);
> +}
> +
> +static const TypeInfo aspeed_otp_info = {
> +    .name          = TYPE_ASPEED_OTP,
> +    .parent        = TYPE_DEVICE,
> +    .instance_size = sizeof(AspeedOTPState),
> +    .class_init    = aspeed_otp_class_init,
> +};
> +
> +static void aspeed_otp_register_types(void)
> +{
> +    type_register_static(&aspeed_otp_info);
> +}
> +
> +type_init(aspeed_otp_register_types)
> diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
> index 10f3639db6..b66f23605b 100644
> --- a/hw/nvram/meson.build
> +++ b/hw/nvram/meson.build
> @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
>   
>   specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
>   specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
> +
> +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> +  'aspeed_otp.c',
> +  ))
> \ No newline at end of file

Hi Cédric,

Got it, I'll rename the type to "aspeed-otp" as suggested to support the global property syntax.

Thanks for the clarification!

Best regards,
Kane

> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, June 30, 2025 2:28 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v3 1/3] hw/misc/aspeed_otp: Add OTP device model with
> fallback RAM storage
> 
> On 6/30/25 07:17, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > This patch introduces a QEMU model of the ASPEED One-Time
> Programmable
> > (OTP) memory, used for secure fuse storage. The model simulates a
> > word-addressable OTP region with a memory-like interface via a
> > dedicated AddressSpace.
> >
> > If no external block backend is provided via the "drive" property, the
> > model automatically allocates an internal RAM-backed storage buffer to
> > hold OTP data, enabling simplified usage without CLI configuration.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> >   include/hw/nvram/aspeed_otp.h |  33 ++++++++++
> >   hw/nvram/aspeed_otp.c         | 113
> ++++++++++++++++++++++++++++++++++
> >   hw/nvram/meson.build          |   4 ++
> >   3 files changed, 150 insertions(+)
> >   create mode 100644 include/hw/nvram/aspeed_otp.h
> >   create mode 100644 hw/nvram/aspeed_otp.c
> >
> > diff --git a/include/hw/nvram/aspeed_otp.h
> > b/include/hw/nvram/aspeed_otp.h new file mode 100644 index
> > 0000000000..22b2195a00
> > --- /dev/null
> > +++ b/include/hw/nvram/aspeed_otp.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + *  ASPEED OTP (One-Time Programmable) memory
> > + *
> > + *  Copyright (C) 2025 Aspeed
> > + *
> > + *  SPDX-License-Identifier: GPL-2.0-or-later  */
> > +
> > +#ifndef ASPEED_OTP_H
> > +#define ASPEED_OTP_H
> > +
> > +#include "system/memory.h"
> > +#include "hw/block/block.h"
> > +#include "system/address-spaces.h"
> > +
> > +#define TYPE_ASPEED_OTP "aspeed.otp"
> 
> Please change to "aspeed-otp" so that we can use :
> 
> 	-global aspeed-otp.drive="foo"
> 
> to define a backend.
> 
> 
> Thanks,
> 
> C.
> 
> 
> 
> > +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
> > +
> > +typedef struct AspeedOTPState {
> > +    DeviceState parent_obj;
> > +
> > +    BlockBackend *blk;
> > +
> > +    uint64_t size;
> > +
> > +    AddressSpace as;
> > +
> > +    MemoryRegion mmio;
> > +
> > +    uint8_t *storage;
> > +} AspeedOTPState;
> > +
> > +#endif /* ASPEED_OTP_H */
> > diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c new file
> > mode 100644 index 0000000000..f018c58713
> > --- /dev/null
> > +++ b/hw/nvram/aspeed_otp.c
> > @@ -0,0 +1,113 @@
> > +/*
> > + *  ASPEED OTP (One-Time Programmable) memory
> > + *
> > + *  Copyright (C) 2025 Aspeed
> > + *
> > + *  SPDX-License-Identifier: GPL-2.0-or-later  */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "qapi/error.h"
> > +#include "system/block-backend-global-state.h"
> > +#include "system/block-backend-io.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/nvram/aspeed_otp.h"
> > +
> > +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned
> > +size) {
> > +    AspeedOTPState *s = opaque;
> > +    uint64_t val = 0;
> > +
> > +    memcpy(&val, s->storage + offset, size);
> > +
> > +    return val;
> > +}
> > +
> > +static void aspeed_otp_write(void *opaque, hwaddr offset,
> > +                                uint64_t val, unsigned size) {
> > +    AspeedOTPState *s = opaque;
> > +
> > +    memcpy(s->storage + offset, &val, size); }
> > +
> > +static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
> > +{
> > +    uint32_t *p;
> > +    int i, num;
> > +    uint64_t perm;
> > +
> > +    if (s->blk) {
> > +        perm = BLK_PERM_CONSISTENT_READ |
> > +               (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE :
> 0);
> > +        if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
> > +            return false;
> > +        }
> > +        if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
> > +            error_setg(errp, "Failed to read the initial flash content");
> > +            return false;
> > +        }
> > +    } else {
> > +        num = s->size / sizeof(uint32_t);
> > +        p = (uint32_t *)s->storage;
> > +        for (i = 0; i < num; i++) {
> > +            p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
> > +        }
> > +    }
> > +    return true;
> > +}
> > +
> > +static const MemoryRegionOps aspeed_otp_ops = {
> > +    .read = aspeed_otp_read,
> > +    .write = aspeed_otp_write,
> > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > +    .valid.min_access_size = 1,
> > +    .valid.max_access_size = 4,
> > +};
> > +
> > +static void aspeed_otp_realize(DeviceState *dev, Error **errp) {
> > +    AspeedOTPState *s = ASPEED_OTP(dev);
> > +
> > +    if (s->size == 0) {
> > +        error_setg(errp, "aspeed.otp: 'size' property must be set");
> > +        return;
> > +    }
> > +
> > +    s->storage = blk_blockalign(s->blk, s->size);
> > +
> > +    if (!aspeed_otp_init_storage(s, errp)) {
> > +        return;
> > +    }
> > +
> > +    memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
> > +                          s, "aspeed.otp", s->size);
> > +    address_space_init(&s->as, &s->mmio, NULL); }
> > +
> > +static const Property aspeed_otp_properties[] = {
> > +    DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
> > +    DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk), };
> > +
> > +static void aspeed_otp_class_init(ObjectClass *klass, const void
> > +*data) {
> > +    DeviceClass *dc = DEVICE_CLASS(klass);
> > +    dc->realize = aspeed_otp_realize;
> > +    device_class_set_props(dc, aspeed_otp_properties); }
> > +
> > +static const TypeInfo aspeed_otp_info = {
> > +    .name          = TYPE_ASPEED_OTP,
> > +    .parent        = TYPE_DEVICE,
> > +    .instance_size = sizeof(AspeedOTPState),
> > +    .class_init    = aspeed_otp_class_init,
> > +};
> > +
> > +static void aspeed_otp_register_types(void) {
> > +    type_register_static(&aspeed_otp_info);
> > +}
> > +
> > +type_init(aspeed_otp_register_types)
> > diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index
> > 10f3639db6..b66f23605b 100644
> > --- a/hw/nvram/meson.build
> > +++ b/hw/nvram/meson.build
> > @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM',
> if_true:
> > files('xlnx-bbram.c'))
> >
> >   specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
> >   specific_ss.add(when: 'CONFIG_ACPI', if_true:
> > files('fw_cfg-acpi.c'))
> > +
> > +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> > +  'aspeed_otp.c',
> > +  ))
> > \ No newline at end of file

On 6/30/25 07:17, Kane Chen wrote:
> From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> 
> This patch introduces a QEMU model of the ASPEED One-Time Programmable
> (OTP) memory, used for secure fuse storage. The model simulates a
> word-addressable OTP region with a memory-like interface via a dedicated
> AddressSpace.
> 
> If no external block backend is provided via the "drive" property, the
> model automatically allocates an internal RAM-backed storage buffer
> to hold OTP data, enabling simplified usage without CLI configuration.
> 
> Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> ---
>   include/hw/nvram/aspeed_otp.h |  33 ++++++++++
>   hw/nvram/aspeed_otp.c         | 113 ++++++++++++++++++++++++++++++++++
>   hw/nvram/meson.build          |   4 ++
>   3 files changed, 150 insertions(+)
>   create mode 100644 include/hw/nvram/aspeed_otp.h
>   create mode 100644 hw/nvram/aspeed_otp.c
> 
> diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h
> new file mode 100644
> index 0000000000..22b2195a00
> --- /dev/null
> +++ b/include/hw/nvram/aspeed_otp.h
> @@ -0,0 +1,33 @@
> +/*
> + *  ASPEED OTP (One-Time Programmable) memory
> + *
> + *  Copyright (C) 2025 Aspeed
> + *
> + *  SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef ASPEED_OTP_H
> +#define ASPEED_OTP_H
> +
> +#include "system/memory.h"
> +#include "hw/block/block.h"
> +#include "system/address-spaces.h"
> +
> +#define TYPE_ASPEED_OTP "aspeed.otp"
> +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
> +
> +typedef struct AspeedOTPState {
> +    DeviceState parent_obj;
> +
> +    BlockBackend *blk;
> +
> +    uint64_t size;
> +
> +    AddressSpace as;
> +
> +    MemoryRegion mmio;
> +
> +    uint8_t *storage;
> +} AspeedOTPState;
> +
> +#endif /* ASPEED_OTP_H */
> diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c
> new file mode 100644
> index 0000000000..f018c58713
> --- /dev/null
> +++ b/hw/nvram/aspeed_otp.c
> @@ -0,0 +1,113 @@
> +/*
> + *  ASPEED OTP (One-Time Programmable) memory
> + *
> + *  Copyright (C) 2025 Aspeed
> + *
> + *  SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "system/block-backend-global-state.h"
> +#include "system/block-backend-io.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/nvram/aspeed_otp.h"
> +
> +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +    AspeedOTPState *s = opaque;
> +    uint64_t val = 0;
> +
> +    memcpy(&val, s->storage + offset, size);
> +
> +    return val;
> +}
> +
> +static void aspeed_otp_write(void *opaque, hwaddr offset,
> +                                uint64_t val, unsigned size)
> +{
> +    AspeedOTPState *s = opaque;
> +
> +    memcpy(s->storage + offset, &val, size);
> +}
> +
> +static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
> +{
> +    uint32_t *p;
> +    int i, num;
> +    uint64_t perm;
> +
> +    if (s->blk) {
> +        perm = BLK_PERM_CONSISTENT_READ |
> +               (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
> +        if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
> +            return false;
> +        }
> +        if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
> +            error_setg(errp, "Failed to read the initial flash content");
> +            return false;
> +        }
> +    } else {
> +        num = s->size / sizeof(uint32_t);
> +        p = (uint32_t *)s->storage;
> +        for (i = 0; i < num; i++) {
> +            p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
> +        }
> +    }
> +    return true;
> +}
> +
> +static const MemoryRegionOps aspeed_otp_ops = {
> +    .read = aspeed_otp_read,
> +    .write = aspeed_otp_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .valid.min_access_size = 1,
> +    .valid.max_access_size = 4,
> +};
> +
> +static void aspeed_otp_realize(DeviceState *dev, Error **errp)
> +{
> +    AspeedOTPState *s = ASPEED_OTP(dev);
> +
> +    if (s->size == 0) {
> +        error_setg(errp, "aspeed.otp: 'size' property must be set");
> +        return;
> +    }
> +
> +    s->storage = blk_blockalign(s->blk, s->size);
> +
> +    if (!aspeed_otp_init_storage(s, errp)) {
> +        return;
> +    }
> +
> +    memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
> +                          s, "aspeed.otp", s->size);
> +    address_space_init(&s->as, &s->mmio, NULL);
> +}
> +
> +static const Property aspeed_otp_properties[] = {
> +    DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
> +    DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk),
> +};
> +
> +static void aspeed_otp_class_init(ObjectClass *klass, const void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    dc->realize = aspeed_otp_realize;
> +    device_class_set_props(dc, aspeed_otp_properties);
> +}
> +
> +static const TypeInfo aspeed_otp_info = {
> +    .name          = TYPE_ASPEED_OTP,
> +    .parent        = TYPE_DEVICE,
> +    .instance_size = sizeof(AspeedOTPState),
> +    .class_init    = aspeed_otp_class_init,
> +};
> +
> +static void aspeed_otp_register_types(void)
> +{
> +    type_register_static(&aspeed_otp_info);
> +}
> +
> +type_init(aspeed_otp_register_types)
> diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
> index 10f3639db6..b66f23605b 100644
> --- a/hw/nvram/meson.build
> +++ b/hw/nvram/meson.build
> @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
>   
>   specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
>   specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
> +
> +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> +  'aspeed_otp.c',
> +  ))
> \ No newline at end of file


The patch looks OK but, in the previous round, I asked to add the
BlockBackend and drive in a new patch. May be I wasn't clear ?

Thanks,

C.

Hi Cédric,

Thanks for pointing that out — sorry for missing your earlier comment.

I'll roll back the BlockBackend and drive part, and send a separate patch for that as suggested.

Best Regards,
Kane
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, June 30, 2025 2:18 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v3 1/3] hw/misc/aspeed_otp: Add OTP device model with
> fallback RAM storage
> 
> On 6/30/25 07:17, Kane Chen wrote:
> > From: Kane-Chen-AS <kane_chen@aspeedtech.com>
> >
> > This patch introduces a QEMU model of the ASPEED One-Time
> Programmable
> > (OTP) memory, used for secure fuse storage. The model simulates a
> > word-addressable OTP region with a memory-like interface via a
> > dedicated AddressSpace.
> >
> > If no external block backend is provided via the "drive" property, the
> > model automatically allocates an internal RAM-backed storage buffer to
> > hold OTP data, enabling simplified usage without CLI configuration.
> >
> > Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com>
> > ---
> >   include/hw/nvram/aspeed_otp.h |  33 ++++++++++
> >   hw/nvram/aspeed_otp.c         | 113
> ++++++++++++++++++++++++++++++++++
> >   hw/nvram/meson.build          |   4 ++
> >   3 files changed, 150 insertions(+)
> >   create mode 100644 include/hw/nvram/aspeed_otp.h
> >   create mode 100644 hw/nvram/aspeed_otp.c
> >
> > diff --git a/include/hw/nvram/aspeed_otp.h
> > b/include/hw/nvram/aspeed_otp.h new file mode 100644 index
> > 0000000000..22b2195a00
> > --- /dev/null
> > +++ b/include/hw/nvram/aspeed_otp.h
> > @@ -0,0 +1,33 @@
> > +/*
> > + *  ASPEED OTP (One-Time Programmable) memory
> > + *
> > + *  Copyright (C) 2025 Aspeed
> > + *
> > + *  SPDX-License-Identifier: GPL-2.0-or-later  */
> > +
> > +#ifndef ASPEED_OTP_H
> > +#define ASPEED_OTP_H
> > +
> > +#include "system/memory.h"
> > +#include "hw/block/block.h"
> > +#include "system/address-spaces.h"
> > +
> > +#define TYPE_ASPEED_OTP "aspeed.otp"
> > +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP)
> > +
> > +typedef struct AspeedOTPState {
> > +    DeviceState parent_obj;
> > +
> > +    BlockBackend *blk;
> > +
> > +    uint64_t size;
> > +
> > +    AddressSpace as;
> > +
> > +    MemoryRegion mmio;
> > +
> > +    uint8_t *storage;
> > +} AspeedOTPState;
> > +
> > +#endif /* ASPEED_OTP_H */
> > diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c new file
> > mode 100644 index 0000000000..f018c58713
> > --- /dev/null
> > +++ b/hw/nvram/aspeed_otp.c
> > @@ -0,0 +1,113 @@
> > +/*
> > + *  ASPEED OTP (One-Time Programmable) memory
> > + *
> > + *  Copyright (C) 2025 Aspeed
> > + *
> > + *  SPDX-License-Identifier: GPL-2.0-or-later  */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "qapi/error.h"
> > +#include "system/block-backend-global-state.h"
> > +#include "system/block-backend-io.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/nvram/aspeed_otp.h"
> > +
> > +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned
> > +size) {
> > +    AspeedOTPState *s = opaque;
> > +    uint64_t val = 0;
> > +
> > +    memcpy(&val, s->storage + offset, size);
> > +
> > +    return val;
> > +}
> > +
> > +static void aspeed_otp_write(void *opaque, hwaddr offset,
> > +                                uint64_t val, unsigned size) {
> > +    AspeedOTPState *s = opaque;
> > +
> > +    memcpy(s->storage + offset, &val, size); }
> > +
> > +static bool aspeed_otp_init_storage(AspeedOTPState *s, Error **errp)
> > +{
> > +    uint32_t *p;
> > +    int i, num;
> > +    uint64_t perm;
> > +
> > +    if (s->blk) {
> > +        perm = BLK_PERM_CONSISTENT_READ |
> > +               (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE :
> 0);
> > +        if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) {
> > +            return false;
> > +        }
> > +        if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) {
> > +            error_setg(errp, "Failed to read the initial flash content");
> > +            return false;
> > +        }
> > +    } else {
> > +        num = s->size / sizeof(uint32_t);
> > +        p = (uint32_t *)s->storage;
> > +        for (i = 0; i < num; i++) {
> > +            p[i] = (i % 2 == 0) ? 0x00000000 : 0xFFFFFFFF;
> > +        }
> > +    }
> > +    return true;
> > +}
> > +
> > +static const MemoryRegionOps aspeed_otp_ops = {
> > +    .read = aspeed_otp_read,
> > +    .write = aspeed_otp_write,
> > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > +    .valid.min_access_size = 1,
> > +    .valid.max_access_size = 4,
> > +};
> > +
> > +static void aspeed_otp_realize(DeviceState *dev, Error **errp) {
> > +    AspeedOTPState *s = ASPEED_OTP(dev);
> > +
> > +    if (s->size == 0) {
> > +        error_setg(errp, "aspeed.otp: 'size' property must be set");
> > +        return;
> > +    }
> > +
> > +    s->storage = blk_blockalign(s->blk, s->size);
> > +
> > +    if (!aspeed_otp_init_storage(s, errp)) {
> > +        return;
> > +    }
> > +
> > +    memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops,
> > +                          s, "aspeed.otp", s->size);
> > +    address_space_init(&s->as, &s->mmio, NULL); }
> > +
> > +static const Property aspeed_otp_properties[] = {
> > +    DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0),
> > +    DEFINE_PROP_DRIVE("drive", AspeedOTPState, blk), };
> > +
> > +static void aspeed_otp_class_init(ObjectClass *klass, const void
> > +*data) {
> > +    DeviceClass *dc = DEVICE_CLASS(klass);
> > +    dc->realize = aspeed_otp_realize;
> > +    device_class_set_props(dc, aspeed_otp_properties); }
> > +
> > +static const TypeInfo aspeed_otp_info = {
> > +    .name          = TYPE_ASPEED_OTP,
> > +    .parent        = TYPE_DEVICE,
> > +    .instance_size = sizeof(AspeedOTPState),
> > +    .class_init    = aspeed_otp_class_init,
> > +};
> > +
> > +static void aspeed_otp_register_types(void) {
> > +    type_register_static(&aspeed_otp_info);
> > +}
> > +
> > +type_init(aspeed_otp_register_types)
> > diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index
> > 10f3639db6..b66f23605b 100644
> > --- a/hw/nvram/meson.build
> > +++ b/hw/nvram/meson.build
> > @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM',
> if_true:
> > files('xlnx-bbram.c'))
> >
> >   specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
> >   specific_ss.add(when: 'CONFIG_ACPI', if_true:
> > files('fw_cfg-acpi.c'))
> > +
> > +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> > +  'aspeed_otp.c',
> > +  ))
> > \ No newline at end of file
> 
> 
> The patch looks OK but, in the previous round, I asked to add the
> BlockBackend and drive in a new patch. May be I wasn't clear ?
> 
> Thanks,
> 
> C.
> 
> 
>