Fix some more RVV source overlap issues

[PATCH v2 0/3] Fix some more RVV source overlap issues

Max Chou posted 3 patches 4 months, 2 weeks ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20250627132022.439315-1-max.chou@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn32.decode              | 10 +++++-----
target/riscv/insn_trans/trans_rvv.c.inc | 26 ++++++++++++++-----------
2 files changed, 20 insertions(+), 16 deletions(-)

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[PATCH v2 0/3] Fix some more RVV source overlap issues

Posted by Max Chou 4 months, 2 weeks ago

This patchset is based on the v1 provided by Anoton Blanchard with
following update:

* Add the missing input EEWs checking rule for widen vector reduction
  instruction.

Reference:
* v1: 20250415043207.3512209-1-antonb@tenstorrent.com

Anton Blanchard (3):
  target/riscv: rvv: Apply vext_check_input_eew to vector integer/fp
    compare instructions
  target/riscv: rvv: Apply vext_check_input_eew to vector reduction
    instructions
  target/riscv: vadc and vsbc are vm=0 instructions

 target/riscv/insn32.decode              | 10 +++++-----
 target/riscv/insn_trans/trans_rvv.c.inc | 26 ++++++++++++++-----------
 2 files changed, 20 insertions(+), 16 deletions(-)

-- 
2.43.0