Per SDM,

80000007H EAX Reserved = 0.
          EBX Reserved = 0.
          ECX Reserved = 0.
          EDX Bits 07-00: Reserved = 0.
              Bit 08: Invariant TSC available if 1.
              Bits 31-09: Reserved = 0.

EAX/EBX/ECX in CPUID 0x80000007 leaf are reserved for Intel.

At present, EAX is reserved for AMD, too. And AMD hasn't used ECX in
QEMU. So these 2 registers are both left as 0.

Therefore, only fix the EBX and excode it as 0 for Intel.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 867e08236540..6d590a9af389 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8374,7 +8374,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
     }
     case 0x80000007:
         *eax = 0;
-        *ebx = env->features[FEAT_8000_0007_EBX];
+        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {
+            *ebx = 0;
+        } else {
+            *ebx = env->features[FEAT_8000_0007_EBX];
+        }
         *ecx = 0;
         *edx = env->features[FEAT_8000_0007_EDX];
         break;
-- 
2.34.1

On 6/27/25 11:51 AM, Zhao Liu wrote:
> 
> Per SDM,
> 
> 80000007H EAX Reserved = 0.
>            EBX Reserved = 0.
>            ECX Reserved = 0.
>            EDX Bits 07-00: Reserved = 0.
>                Bit 08: Invariant TSC available if 1.
>                Bits 31-09: Reserved = 0.
> 
> EAX/EBX/ECX in CPUID 0x80000007 leaf are reserved for Intel.
> 
> At present, EAX is reserved for AMD, too. And AMD hasn't used ECX in
> QEMU. So these 2 registers are both left as 0.
> 
> Therefore, only fix the EBX and excode it as 0 for Intel.
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
>   target/i386/cpu.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 867e08236540..6d590a9af389 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -8374,7 +8374,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>       }
>       case 0x80000007:
>           *eax = 0;
> -        *ebx = env->features[FEAT_8000_0007_EBX];
> +        if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) {

Please add IS_ZHAOXIN_CPU(env), because Zhaoxin follows the SDM definition for 
CPUID leaf 0x80000008.

> +            *ebx = 0;
> +        } else {
> +            *ebx = env->features[FEAT_8000_0007_EBX];
> +        }
>           *ecx = 0;
>           *edx = env->features[FEAT_8000_0007_EDX];
>           break;
> --
> 2.34.1
>