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[PATCH v3 8/9] target/loongarch: CPU enable msg interrupts.

Song Gao posted 9 patches 4 months, 3 weeks ago
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>, Jiaxun Yang <jiaxun.yang@flygoat.com>
There is a newer version of this series
[PATCH v3 8/9] target/loongarch: CPU enable msg interrupts.
Posted by Song Gao 4 months, 3 weeks ago 
when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
and CSR_ECFG.MSGINT bit.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu-csr.h |  6 ++++--
 target/loongarch/cpu.c     | 10 ++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 4792677086..6ec13d13d1 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -34,11 +34,13 @@ FIELD(CSR_MISC, ALCL, 12, 4)
 FIELD(CSR_MISC, DWPL, 16, 3)
 
 #define LOONGARCH_CSR_ECFG           0x4 /* Exception config */
-FIELD(CSR_ECFG, LIE, 0, 13)
+FIELD(CSR_ECFG, LIE, 0, 15)        /*bit 15 is msg interrupt enabled */
+FIELD(CSR_ECFG, MSGINT, 14, 1)
 FIELD(CSR_ECFG, VS, 16, 3)
 
 #define LOONGARCH_CSR_ESTAT          0x5 /* Exception status */
-FIELD(CSR_ESTAT, IS, 0, 13)
+FIELD(CSR_ESTAT, IS, 0, 15)        /*bit 15 is msg interrupt enabled */
+FIELD(CSR_ESTAT, MSGINT, 14, 1)
 FIELD(CSR_ESTAT, ECODE, 16, 6)
 FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
 
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index bde9f917fc..c5924bb94f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -127,6 +127,16 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
         return;
     }
 
+    /* do INTC_AVEC irqs */
+    if (irq == INT_AVEC) {
+        for (int i = 256; i >= 0; i--) {
+            if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) {
+                env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
+                env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);
+            }
+        }
+    }
+
     if (kvm_enabled()) {
         kvm_loongarch_set_interrupt(cpu, irq, level);
     } else if (tcg_enabled()) {
-- 
2.34.1
Re: [PATCH v3 8/9] target/loongarch: CPU enable msg interrupts.
Posted by Bibo Mao 4 months, 2 weeks ago 

On 2025/6/27 上午11:01, Song Gao wrote:
> when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
> and CSR_ECFG.MSGINT bit.
> 
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/cpu-csr.h |  6 ++++--
>   target/loongarch/cpu.c     | 10 ++++++++++
>   2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index 4792677086..6ec13d13d1 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -34,11 +34,13 @@ FIELD(CSR_MISC, ALCL, 12, 4)
>   FIELD(CSR_MISC, DWPL, 16, 3)
>   
>   #define LOONGARCH_CSR_ECFG           0x4 /* Exception config */
> -FIELD(CSR_ECFG, LIE, 0, 13)
> +FIELD(CSR_ECFG, LIE, 0, 15)        /*bit 15 is msg interrupt enabled */
> +FIELD(CSR_ECFG, MSGINT, 14, 1)
>   FIELD(CSR_ECFG, VS, 16, 3)
>   
>   #define LOONGARCH_CSR_ESTAT          0x5 /* Exception status */
> -FIELD(CSR_ESTAT, IS, 0, 13)
> +FIELD(CSR_ESTAT, IS, 0, 15)        /*bit 15 is msg interrupt enabled */
> +FIELD(CSR_ESTAT, MSGINT, 14, 1)
>   FIELD(CSR_ESTAT, ECODE, 16, 6)
>   FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
>   
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index bde9f917fc..c5924bb94f 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -127,6 +127,16 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
>           return;
>       }
>   
> +    /* do INTC_AVEC irqs */
> +    if (irq == INT_AVEC) {
> +        for (int i = 256; i >= 0; i--) {
> +            if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) {
> +                env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
> +                env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);
> +            }
> +        }
> +    }
I think it can be simplified as follows:
   /* do INTC_AVEC irqs */
   if (irq == INT_AVEC) {
       env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
       env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);
   }

Regards
Bibo Mao
> +
>       if (kvm_enabled()) {
>           kvm_loongarch_set_interrupt(cpu, irq, level);
>       } else if (tcg_enabled()) {
>
Re: [PATCH v3 8/9] target/loongarch: CPU enable msg interrupts.
Posted by gaosong 4 months, 2 weeks ago 
在 2025/7/2 上午11:20, Bibo Mao 写道:
>
>
> On 2025/6/27 上午11:01, Song Gao wrote:
>> when loongarch cpu set irq is INT_AVEC, we need set CSR_ESTAT.MSGINT bit
>> and CSR_ECFG.MSGINT bit.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>   target/loongarch/cpu-csr.h |  6 ++++--
>>   target/loongarch/cpu.c     | 10 ++++++++++
>>   2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index 4792677086..6ec13d13d1 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -34,11 +34,13 @@ FIELD(CSR_MISC, ALCL, 12, 4)
>>   FIELD(CSR_MISC, DWPL, 16, 3)
>>     #define LOONGARCH_CSR_ECFG           0x4 /* Exception config */
>> -FIELD(CSR_ECFG, LIE, 0, 13)
>> +FIELD(CSR_ECFG, LIE, 0, 15)        /*bit 15 is msg interrupt enabled */
>> +FIELD(CSR_ECFG, MSGINT, 14, 1)
>>   FIELD(CSR_ECFG, VS, 16, 3)
>>     #define LOONGARCH_CSR_ESTAT          0x5 /* Exception status */
>> -FIELD(CSR_ESTAT, IS, 0, 13)
>> +FIELD(CSR_ESTAT, IS, 0, 15)        /*bit 15 is msg interrupt enabled */
>> +FIELD(CSR_ESTAT, MSGINT, 14, 1)
>>   FIELD(CSR_ESTAT, ECODE, 16, 6)
>>   FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
>>   diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index bde9f917fc..c5924bb94f 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -127,6 +127,16 @@ void loongarch_cpu_set_irq(void *opaque, int 
>> irq, int level)
>>           return;
>>       }
>>   +    /* do INTC_AVEC irqs */
>> +    if (irq == INT_AVEC) {
>> +        for (int i = 256; i >= 0; i--) {
>> +            if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) {
>> +                env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, 
>> CSR_ESTAT, MSGINT, 1);
>> +                env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, 
>> MSGINT, 1);
>> +            }
>> +        }
>> +    }
> I think it can be simplified as follows:
>   /* do INTC_AVEC irqs */
>   if (irq == INT_AVEC) {
>       env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 1);
>       env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 1);
>   }
>
Got it.  I will corrrect it on v3 .  thanks for your suggestions and 
comments.

Thanks.
Song Gao
> Regards
> Bibo Mao
>> +
>>       if (kvm_enabled()) {
>>           kvm_loongarch_set_interrupt(cpu, irq, level);
>>       } else if (tcg_enabled()) {
>>

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