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[PATCH v3 4/9] target/loongarch: add msg interrupt CSR registers

Song Gao posted 9 patches 7 months, 2 weeks ago
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>, Jiaxun Yang <jiaxun.yang@flygoat.com>
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[PATCH v3 4/9] target/loongarch: add msg interrupt CSR registers
Posted by Song Gao 7 months, 2 weeks ago 
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/cpu-csr.h |  3 +++
 target/loongarch/cpu.c     |  7 +++++++
 target/loongarch/cpu.h     | 10 ++++++++++
 target/loongarch/machine.c | 25 +++++++++++++++++++++++--
 4 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f30..4792677086 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -186,6 +186,9 @@ FIELD(CSR_MERRCTL, ISMERR, 0, 1)
 
 #define LOONGARCH_CSR_CTAG           0x98 /* TagLo + TagHi */
 
+#define LOONGARCH_CSR_MSGIS(N)       (0xa0 + N)
+#define LOONGARCH_CSR_MSGIR               0xa4
+
 /* Direct map windows CSRs*/
 #define LOONGARCH_CSR_DMW(N)         (0x180 + N)
 FIELD(CSR_DMW, PLV0, 0, 1)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index abad84c054..bde9f917fc 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -523,6 +523,13 @@ static void loongarch_la464_initfn(Object *obj)
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
     env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
 
+    env->CSR_MSGIS[0] = 0;
+    env->CSR_MSGIS[1] = 0;
+    env->CSR_MSGIS[2] = 0;
+    env->CSR_MSGIS[3] = 0;
+    env->CSR_MSGIR = 0;
+    env->CSR_MSGIE = 0;
+
     loongarch_la464_init_csr(obj);
     loongarch_cpu_post_init(obj);
 }
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 56fc4a1459..208d3e0cd3 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -233,6 +233,12 @@ FIELD(TLB_MISC, ASID, 1, 10)
 FIELD(TLB_MISC, VPPN, 13, 35)
 FIELD(TLB_MISC, PS, 48, 6)
 
+/*Msg interrupt registers */
+FIELD(CSR_MSGIS, IS, 0, 63)
+FIELD(CSR_MSGIR, INTNUM, 0, 8)
+FIELD(CSR_MSGIR, ACTIVE, 31, 1)
+FIELD(CSR_MSGIE, PT, 0, 8)
+
 #define LSX_LEN    (128)
 #define LASX_LEN   (256)
 
@@ -350,6 +356,10 @@ typedef struct CPUArchState {
     uint64_t CSR_DBG;
     uint64_t CSR_DERA;
     uint64_t CSR_DSAVE;
+    /* Msg interrupt registers */
+    uint64_t CSR_MSGIS[4];
+    uint64_t CSR_MSGIR;
+    uint64_t CSR_MSGIE;
     struct {
         uint64_t guest_addr;
     } stealtime;
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 4e70f5c879..1e276c08ac 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -45,6 +45,26 @@ static const VMStateDescription vmstate_fpu = {
     },
 };
 
+static bool msg_needed(void *opaque)
+{
+    LoongArchCPU *cpu = opaque;
+
+    return FIELD_EX64(cpu->env.cpucfg[1], CPUCFG1, MSG_INT);
+}
+
+static const VMStateDescription vmstate_msg = {
+    .name = "cpu/msg",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = msg_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4),
+        VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU),
+        VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
 static const VMStateDescription vmstate_lsxh_reg = {
     .name = "lsxh_reg",
     .version_id = 1,
@@ -168,8 +188,8 @@ static const VMStateDescription vmstate_tlb = {
 /* LoongArch CPU state */
 const VMStateDescription vmstate_loongarch_cpu = {
     .name = "cpu",
-    .version_id = 3,
-    .minimum_version_id = 3,
+    .version_id = 4,
+    .minimum_version_id = 4,
     .fields = (const VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
         VMSTATE_UINTTL(env.pc, LoongArchCPU),
@@ -245,6 +265,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
         &vmstate_tlb,
 #endif
         &vmstate_lbt,
+        &vmstate_msg,
         NULL
     }
 };
-- 
2.34.1
Re: [PATCH v3 4/9] target/loongarch: add msg interrupt CSR registers
Posted by Bibo Mao 7 months, 1 week ago 

On 2025/6/27 上午11:01, Song Gao wrote:
> include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
> 
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/cpu-csr.h |  3 +++
>   target/loongarch/cpu.c     |  7 +++++++
>   target/loongarch/cpu.h     | 10 ++++++++++
>   target/loongarch/machine.c | 25 +++++++++++++++++++++++--
>   4 files changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
> index 0834e91f30..4792677086 100644
> --- a/target/loongarch/cpu-csr.h
> +++ b/target/loongarch/cpu-csr.h
> @@ -186,6 +186,9 @@ FIELD(CSR_MERRCTL, ISMERR, 0, 1)
>   
>   #define LOONGARCH_CSR_CTAG           0x98 /* TagLo + TagHi */
>   
> +#define LOONGARCH_CSR_MSGIS(N)       (0xa0 + N)
> +#define LOONGARCH_CSR_MSGIR               0xa4
> +
>   /* Direct map windows CSRs*/
>   #define LOONGARCH_CSR_DMW(N)         (0x180 + N)
>   FIELD(CSR_DMW, PLV0, 0, 1)
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index abad84c054..bde9f917fc 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -523,6 +523,13 @@ static void loongarch_la464_initfn(Object *obj)
>       env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
>       env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
>   
> +    env->CSR_MSGIS[0] = 0;
> +    env->CSR_MSGIS[1] = 0;
> +    env->CSR_MSGIS[2] = 0;
> +    env->CSR_MSGIS[3] = 0;
> +    env->CSR_MSGIR = 0;
> +    env->CSR_MSGIE = 0;
> +
The default value should zero for CSR register, I think it can be 
removed here.

>       loongarch_la464_init_csr(obj);
>       loongarch_cpu_post_init(obj);
>   }
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 56fc4a1459..208d3e0cd3 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -233,6 +233,12 @@ FIELD(TLB_MISC, ASID, 1, 10)
>   FIELD(TLB_MISC, VPPN, 13, 35)
>   FIELD(TLB_MISC, PS, 48, 6)
>   
> +/*Msg interrupt registers */
> +FIELD(CSR_MSGIS, IS, 0, 63)
> +FIELD(CSR_MSGIR, INTNUM, 0, 8)
> +FIELD(CSR_MSGIR, ACTIVE, 31, 1)
> +FIELD(CSR_MSGIE, PT, 0, 8)
> +
>   #define LSX_LEN    (128)
>   #define LASX_LEN   (256)
>   
> @@ -350,6 +356,10 @@ typedef struct CPUArchState {
>       uint64_t CSR_DBG;
>       uint64_t CSR_DERA;
>       uint64_t CSR_DSAVE;
> +    /* Msg interrupt registers */
> +    uint64_t CSR_MSGIS[4];
> +    uint64_t CSR_MSGIR;
> +    uint64_t CSR_MSGIE;
>       struct {
>           uint64_t guest_addr;
>       } stealtime;
> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
> index 4e70f5c879..1e276c08ac 100644
> --- a/target/loongarch/machine.c
> +++ b/target/loongarch/machine.c
> @@ -45,6 +45,26 @@ static const VMStateDescription vmstate_fpu = {
>       },
>   };
>   
> +static bool msg_needed(void *opaque)
> +{
> +    LoongArchCPU *cpu = opaque;
> +
> +    return FIELD_EX64(cpu->env.cpucfg[1], CPUCFG1, MSG_INT);
For AVEC capability, there is bit MSG_INT in register cpucfg1 and bit 
IOCSRF_AVEC in IOCSR FEATURE_REG register. Which should be used by real 
hardware?

Regards
Bibo Mao
> +}
> +
> +static const VMStateDescription vmstate_msg = {
> +    .name = "cpu/msg",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = msg_needed,
> +    .fields = (const VMStateField[]) {
> +        VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4),
> +        VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU),
> +        VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU),
> +        VMSTATE_END_OF_LIST()
> +    },
> +};
> +
>   static const VMStateDescription vmstate_lsxh_reg = {
>       .name = "lsxh_reg",
>       .version_id = 1,
> @@ -168,8 +188,8 @@ static const VMStateDescription vmstate_tlb = {
>   /* LoongArch CPU state */
>   const VMStateDescription vmstate_loongarch_cpu = {
>       .name = "cpu",
> -    .version_id = 3,
> -    .minimum_version_id = 3,
> +    .version_id = 4,
> +    .minimum_version_id = 4,
>       .fields = (const VMStateField[]) {
>           VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
>           VMSTATE_UINTTL(env.pc, LoongArchCPU),
> @@ -245,6 +265,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
>           &vmstate_tlb,
>   #endif
>           &vmstate_lbt,
> +        &vmstate_msg,
>           NULL
>       }
>   };
>
Re: [PATCH v3 4/9] target/loongarch: add msg interrupt CSR registers
Posted by gaosong 7 months, 1 week ago 
在 2025/7/2 上午10:24, Bibo Mao 写道:
>
>
> On 2025/6/27 上午11:01, Song Gao wrote:
>> include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>   target/loongarch/cpu-csr.h |  3 +++
>>   target/loongarch/cpu.c     |  7 +++++++
>>   target/loongarch/cpu.h     | 10 ++++++++++
>>   target/loongarch/machine.c | 25 +++++++++++++++++++++++--
>>   4 files changed, 43 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
>> index 0834e91f30..4792677086 100644
>> --- a/target/loongarch/cpu-csr.h
>> +++ b/target/loongarch/cpu-csr.h
>> @@ -186,6 +186,9 @@ FIELD(CSR_MERRCTL, ISMERR, 0, 1)
>>     #define LOONGARCH_CSR_CTAG           0x98 /* TagLo + TagHi */
>>   +#define LOONGARCH_CSR_MSGIS(N)       (0xa0 + N)
>> +#define LOONGARCH_CSR_MSGIR               0xa4
>> +
>>   /* Direct map windows CSRs*/
>>   #define LOONGARCH_CSR_DMW(N)         (0x180 + N)
>>   FIELD(CSR_DMW, PLV0, 0, 1)
>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
>> index abad84c054..bde9f917fc 100644
>> --- a/target/loongarch/cpu.c
>> +++ b/target/loongarch/cpu.c
>> @@ -523,6 +523,13 @@ static void loongarch_la464_initfn(Object *obj)
>>       env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, 
>> STLB_WAYS, 7);
>>       env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, 
>> STLB_SETS, 8);
>>   +    env->CSR_MSGIS[0] = 0;
>> +    env->CSR_MSGIS[1] = 0;
>> +    env->CSR_MSGIS[2] = 0;
>> +    env->CSR_MSGIS[3] = 0;
>> +    env->CSR_MSGIR = 0;
>> +    env->CSR_MSGIE = 0;
>> +
> The default value should zero for CSR register, I think it can be 
> removed here.
>
yes.
>>       loongarch_la464_init_csr(obj);
>>       loongarch_cpu_post_init(obj);
>>   }
>> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
>> index 56fc4a1459..208d3e0cd3 100644
>> --- a/target/loongarch/cpu.h
>> +++ b/target/loongarch/cpu.h
>> @@ -233,6 +233,12 @@ FIELD(TLB_MISC, ASID, 1, 10)
>>   FIELD(TLB_MISC, VPPN, 13, 35)
>>   FIELD(TLB_MISC, PS, 48, 6)
>>   +/*Msg interrupt registers */
>> +FIELD(CSR_MSGIS, IS, 0, 63)
>> +FIELD(CSR_MSGIR, INTNUM, 0, 8)
>> +FIELD(CSR_MSGIR, ACTIVE, 31, 1)
>> +FIELD(CSR_MSGIE, PT, 0, 8)
>> +
>>   #define LSX_LEN    (128)
>>   #define LASX_LEN   (256)
>>   @@ -350,6 +356,10 @@ typedef struct CPUArchState {
>>       uint64_t CSR_DBG;
>>       uint64_t CSR_DERA;
>>       uint64_t CSR_DSAVE;
>> +    /* Msg interrupt registers */
>> +    uint64_t CSR_MSGIS[4];
>> +    uint64_t CSR_MSGIR;
>> +    uint64_t CSR_MSGIE;
>>       struct {
>>           uint64_t guest_addr;
>>       } stealtime;
>> diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
>> index 4e70f5c879..1e276c08ac 100644
>> --- a/target/loongarch/machine.c
>> +++ b/target/loongarch/machine.c
>> @@ -45,6 +45,26 @@ static const VMStateDescription vmstate_fpu = {
>>       },
>>   };
>>   +static bool msg_needed(void *opaque)
>> +{
>> +    LoongArchCPU *cpu = opaque;
>> +
>> +    return FIELD_EX64(cpu->env.cpucfg[1], CPUCFG1, MSG_INT);
> For AVEC capability, there is bit MSG_INT in register cpucfg1 and bit 
> IOCSRF_AVEC in IOCSR FEATURE_REG register. Which should be used by 
> real hardware?
>
they use IOCSR bit, so  I will correct on v3 .
Thanks.
Song Gao
> Regards
> Bibo Mao
>> +}
>> +
>> +static const VMStateDescription vmstate_msg = {
>> +    .name = "cpu/msg",
>> +    .version_id = 1,
>> +    .minimum_version_id = 1,
>> +    .needed = msg_needed,
>> +    .fields = (const VMStateField[]) {
>> +        VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4),
>> +        VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU),
>> +        VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU),
>> +        VMSTATE_END_OF_LIST()
>> +    },
>> +};
>> +
>>   static const VMStateDescription vmstate_lsxh_reg = {
>>       .name = "lsxh_reg",
>>       .version_id = 1,
>> @@ -168,8 +188,8 @@ static const VMStateDescription vmstate_tlb = {
>>   /* LoongArch CPU state */
>>   const VMStateDescription vmstate_loongarch_cpu = {
>>       .name = "cpu",
>> -    .version_id = 3,
>> -    .minimum_version_id = 3,
>> +    .version_id = 4,
>> +    .minimum_version_id = 4,
>>       .fields = (const VMStateField[]) {
>>           VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
>>           VMSTATE_UINTTL(env.pc, LoongArchCPU),
>> @@ -245,6 +265,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
>>           &vmstate_tlb,
>>   #endif
>>           &vmstate_lbt,
>> +        &vmstate_msg,
>>           NULL
>>       }
>>   };
>>

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