Add the cache model to SierraForest (v3) to better emulate its
environment.
The cache model is based on SierraForest-SP (Scalable Performance):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x0 (0)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x80 (128)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 128
(size synth) = 65536 (64 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x7 (7)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x10 (16)
number of sets = 0x1000 (4096)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 4096
(size synth) = 4194304 (4 MB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1ff (511)
maximum IDs for cores in pkg = 0x3f (63)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0xc (12)
number of sets = 0x24000 (147456)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = true
number of sets (s) = 147456
(size synth) = 113246208 (108 MB)
--- cache 4 ---
cache type = no more caches (0)
Suggested-by: Tejus GK <tejus.gk@nutanix.com>
Suggested-by: Jason Zeng <jason.zeng@intel.com>
Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 28e5b7859fef..fcaa2625b023 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2883,6 +2883,97 @@ static const CPUCaches epyc_turin_cache_info = {
.no_invd_sharing = true,
.complex_indexing = false,
.share_level = CPU_TOPOLOGY_LEVEL_DIE,
+ }
+};
+
+static const CPUCaches xeon_srf_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x0.EAX */
+ .type = DATA_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x0.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x0.ECX */
+ .sets = 64,
+
+ /* CPUID 0x4.0x0.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 32 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x1.EAX */
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .self_init = true,
+
+ /* CPUID 0x4.0x1.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 8,
+
+ /* CPUID 0x4.0x1.ECX */
+ .sets = 128,
+
+ /* CPUID 0x4.0x1.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 64 * KiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x2.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .self_init = true,
+
+ /* CPUID 0x4.0x2.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 16,
+
+ /* CPUID 0x4.0x2.ECX */
+ .sets = 4096,
+
+ /* CPUID 0x4.0x2.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = false,
+
+ .size = 4 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_MODULE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ /* CPUID 0x4.0x3.EAX */
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .self_init = true,
+
+ /* CPUID 0x4.0x3.EBX */
+ .line_size = 64,
+ .partitions = 1,
+ .associativity = 12,
+
+ /* CPUID 0x4.0x3.ECX */
+ .sets = 147456,
+
+ /* CPUID 0x4.0x3.EDX */
+ .no_invd_sharing = false,
+ .inclusive = false,
+ .complex_indexing = true,
+
+ .size = 108 * MiB,
+ .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
},
};
@@ -5008,6 +5099,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .note = "with srf-sp cache model",
+ .cache_info = &xeon_srf_cache_info,
+ },
{ /* end of list */ },
},
},
--
2.34.1
On Thu, Jun 26, 2025 at 04:30:58PM +0800, Zhao Liu wrote:
> Add the cache model to SierraForest (v3) to better emulate its
> environment.
>
> The cache model is based on SierraForest-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
> cache level = 0x1 (1)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x0 (0)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x8 (8)
> number of sets = 0x40 (64)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 64
> (size synth) = 32768 (32 KB)
> --- cache 1 ---
> cache type = instruction cache (2)
> cache level = 0x1 (1)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x0 (0)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x8 (8)
> number of sets = 0x80 (128)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 128
> (size synth) = 65536 (64 KB)
> --- cache 2 ---
> cache type = unified cache (3)
> cache level = 0x2 (2)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x7 (7)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x10 (16)
> number of sets = 0x1000 (4096)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 4096
> (size synth) = 4194304 (4 MB)
> --- cache 3 ---
> cache type = unified cache (3)
> cache level = 0x3 (3)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x1ff (511)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0xc (12)
> number of sets = 0x24000 (147456)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = true
> number of sets (s) = 147456
> (size synth) = 113246208 (108 MB)
> --- cache 4 ---
> cache type = no more caches (0)
>
> Suggested-by: Tejus GK <tejus.gk@nutanix.com>
> Suggested-by: Jason Zeng <jason.zeng@intel.com>
> Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 28e5b7859fef..fcaa2625b023 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2883,6 +2883,97 @@ static const CPUCaches epyc_turin_cache_info = {
> .no_invd_sharing = true,
> .complex_indexing = false,
> .share_level = CPU_TOPOLOGY_LEVEL_DIE,
> + }
> +};
> +
> +static const CPUCaches xeon_srf_cache_info = {
> + .l1d_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x0.EAX */
> + .type = DATA_CACHE,
> + .level = 1,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x0.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 8,
> +
> + /* CPUID 0x4.0x0.ECX */
> + .sets = 64,
> +
> + /* CPUID 0x4.0x0.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 32 * KiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l1i_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x1.EAX */
> + .type = INSTRUCTION_CACHE,
> + .level = 1,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x1.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 8,
> +
> + /* CPUID 0x4.0x1.ECX */
> + .sets = 128,
> +
> + /* CPUID 0x4.0x1.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 64 * KiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l2_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x2.EAX */
> + .type = UNIFIED_CACHE,
> + .level = 2,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x2.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 16,
> +
> + /* CPUID 0x4.0x2.ECX */
> + .sets = 4096,
> +
> + /* CPUID 0x4.0x2.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 4 * MiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_MODULE,
> + },
> + .l3_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x3.EAX */
> + .type = UNIFIED_CACHE,
> + .level = 3,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x3.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 12,
> +
> + /* CPUID 0x4.0x3.ECX */
> + .sets = 147456,
> +
> + /* CPUID 0x4.0x3.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = true,
> +
> + .size = 108 * MiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
> },
> };
>
> @@ -5008,6 +5099,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> }
> },
> + {
> + .version = 3,
> + .note = "with srf-sp cache model",
> + .cache_info = &xeon_srf_cache_info,
> + },
> { /* end of list */ },
> },
> },
Reviewed-by: Tao Su <tao1.su@linux.intel.com>
> --
> 2.34.1
>
>
On 6/26/2025 4:30 PM, Zhao Liu wrote:
> Add the cache model to SierraForest (v3) to better emulate its
> environment.
>
> The cache model is based on SierraForest-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
> cache level = 0x1 (1)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x0 (0)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x8 (8)
> number of sets = 0x40 (64)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 64
> (size synth) = 32768 (32 KB)
> --- cache 1 ---
> cache type = instruction cache (2)
> cache level = 0x1 (1)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x0 (0)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x8 (8)
> number of sets = 0x80 (128)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 128
> (size synth) = 65536 (64 KB)
> --- cache 2 ---
> cache type = unified cache (3)
> cache level = 0x2 (2)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x7 (7)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0x10 (16)
> number of sets = 0x1000 (4096)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = false
> number of sets (s) = 4096
> (size synth) = 4194304 (4 MB)
> --- cache 3 ---
> cache type = unified cache (3)
> cache level = 0x3 (3)
> self-initializing cache level = true
> fully associative cache = false
> maximum IDs for CPUs sharing cache = 0x1ff (511)
> maximum IDs for cores in pkg = 0x3f (63)
> system coherency line size = 0x40 (64)
> physical line partitions = 0x1 (1)
> ways of associativity = 0xc (12)
> number of sets = 0x24000 (147456)
> WBINVD/INVD acts on lower caches = false
> inclusive to lower caches = false
> complex cache indexing = true
> number of sets (s) = 147456
> (size synth) = 113246208 (108 MB)
> --- cache 4 ---
> cache type = no more caches (0)
>
> Suggested-by: Tejus GK <tejus.gk@nutanix.com>
> Suggested-by: Jason Zeng <jason.zeng@intel.com>
> Suggested-by: "Daniel P . Berrangé" <berrange@redhat.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 28e5b7859fef..fcaa2625b023 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2883,6 +2883,97 @@ static const CPUCaches epyc_turin_cache_info = {
> .no_invd_sharing = true,
> .complex_indexing = false,
> .share_level = CPU_TOPOLOGY_LEVEL_DIE,
> + }
> +};
> +
> +static const CPUCaches xeon_srf_cache_info = {
> + .l1d_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x0.EAX */
> + .type = DATA_CACHE,
> + .level = 1,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x0.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 8,
> +
> + /* CPUID 0x4.0x0.ECX */
> + .sets = 64,
> +
> + /* CPUID 0x4.0x0.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 32 * KiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l1i_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x1.EAX */
> + .type = INSTRUCTION_CACHE,
> + .level = 1,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x1.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 8,
> +
> + /* CPUID 0x4.0x1.ECX */
> + .sets = 128,
> +
> + /* CPUID 0x4.0x1.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 64 * KiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l2_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x2.EAX */
> + .type = UNIFIED_CACHE,
> + .level = 2,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x2.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 16,
> +
> + /* CPUID 0x4.0x2.ECX */
> + .sets = 4096,
> +
> + /* CPUID 0x4.0x2.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = false,
> +
> + .size = 4 * MiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_MODULE,
> + },
> + .l3_cache = &(CPUCacheInfo) {
> + /* CPUID 0x4.0x3.EAX */
> + .type = UNIFIED_CACHE,
> + .level = 3,
> + .self_init = true,
> +
> + /* CPUID 0x4.0x3.EBX */
> + .line_size = 64,
> + .partitions = 1,
> + .associativity = 12,
> +
> + /* CPUID 0x4.0x3.ECX */
> + .sets = 147456,
> +
> + /* CPUID 0x4.0x3.EDX */
> + .no_invd_sharing = false,
> + .inclusive = false,
> + .complex_indexing = true,
> +
> + .size = 108 * MiB,
> + .share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
> },
> };
>
> @@ -5008,6 +5099,11 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> }
> },
> + {
> + .version = 3,
> + .note = "with srf-sp cache model",
> + .cache_info = &xeon_srf_cache_info,
> + },
> { /* end of list */ },
> },
> },
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
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