[v1] Add QEMU model for ASPEED OTP memory and integrate with SoC

[PATCH v1 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

Kane Chen via posted 3 patches 4 months, 3 weeks ago

Diff against v2 v3 v6
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20250626075711.1589039-1-kane._5Fchen@aspeedtech.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>

There is a newer version of this series

include/hw/misc/aspeed_otpmem.h |  33 +++++++++
include/hw/misc/aspeed_sbc.h    |   5 ++
hw/arm/aspeed_ast2600.c         |   2 +-
hw/misc/aspeed_otpmem.c         |  91 +++++++++++++++++++++++++
hw/misc/aspeed_sbc.c            | 115 ++++++++++++++++++++++++++++++++
hw/misc/meson.build             |   1 +
hw/misc/trace-events            |   5 ++
7 files changed, 251 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/aspeed_otpmem.h
create mode 100644 hw/misc/aspeed_otpmem.c

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[PATCH v1 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

Posted by Kane Chen via 4 months, 3 weeks ago

From: Kane-Chen-AS <kane_chen@aspeedtech.com>

This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).

The OTP model emulates a simple fuse array used for secure boot or
device configuration, implemented with internal buffers; external
file/device support not included in this version. It exposes an
AddressSpace to support transaction-based access from controllers
like the SBC.

This series includes:
  - OTP memory device implementation
  - SBC integration with command decoding (READ/PROG)
  - Direct integration in AST2600 SoC without requiring user parameters

Any feedback or suggestions are appreciated!

---

Kane-Chen-AS (3):
  hw/misc/aspeed_otp: Add ASPEED OTP memory device model
  hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
  hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs

 include/hw/misc/aspeed_otpmem.h |  33 +++++++++
 include/hw/misc/aspeed_sbc.h    |   5 ++
 hw/arm/aspeed_ast2600.c         |   2 +-
 hw/misc/aspeed_otpmem.c         |  91 +++++++++++++++++++++++++
 hw/misc/aspeed_sbc.c            | 115 ++++++++++++++++++++++++++++++++
 hw/misc/meson.build             |   1 +
 hw/misc/trace-events            |   5 ++
 7 files changed, 251 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/misc/aspeed_otpmem.h
 create mode 100644 hw/misc/aspeed_otpmem.c

-- 
2.43.0