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[PATCH v4 07/11] target/riscv: Add Xmipslsp instructions

Djordje Todorovic posted 11 patches 4 months, 3 weeks ago
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Paolo Bonzini <pbonzini@redhat.com>, "Michael S. Tsirkin" <mst@redhat.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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[PATCH v4 07/11] target/riscv: Add Xmipslsp instructions
Posted by Djordje Todorovic 4 months, 3 weeks ago 
Add MIPS P8700 ldp, lwp, sdp, swp instructions.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu.c                        |  3 +
 target/riscv/cpu_cfg.h                    |  3 +-
 target/riscv/cpu_cfg_fields.h.inc         |  1 +
 target/riscv/insn_trans/trans_xmips.c.inc | 84 +++++++++++++++++++++++
 target/riscv/xmips.decode                 | 23 +++++++
 5 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e5194fd06..6e3514a713 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -232,6 +232,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
     ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop),
     ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
+    ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp),
     ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
     ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
     ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -1364,6 +1365,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
     MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
     MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
     MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
+    MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false),
 
     { },
 };
@@ -3182,6 +3184,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .cfg.pmp = true,
         .cfg.ext_zba = true,
         .cfg.ext_zbb = true,
+        .cfg.ext_xmipslsp = true,
         .cfg.ext_xmipscbop = true,
         .cfg.ext_xmipscmov = true,
         .cfg.marchid = 0x8000000000000201,
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 9734963035..cd1cba797c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -22,7 +22,6 @@
 #define RISCV_CPU_CFG_H
 
 struct RISCVCPUConfig {
-
 #define BOOL_FIELD(x) bool x;
 #define TYPED_FIELD(type, x, default) type x;
 #include "cpu_cfg_fields.h.inc"
@@ -39,7 +38,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
 
 static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
 {
-    return cfg->ext_xmipscbop || cfg->ext_xmipscmov;
+    return cfg->ext_xmipscbop || cfg->ext_xmipscmov || cfg->ext_xmipslsp;
 }
 
 static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 9ee0a099bb..b5195959b2 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadsync)
 BOOL_FIELD(ext_XVentanaCondOps)
 BOOL_FIELD(ext_xmipscbop)
 BOOL_FIELD(ext_xmipscmov)
+BOOL_FIELD(ext_xmipslsp)
 
 BOOL_FIELD(mmu)
 BOOL_FIELD(pmp)
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
index 6555a6062a..d2720a6770 100644
--- a/target/riscv/insn_trans/trans_xmips.c.inc
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -31,6 +31,12 @@
     }                                            \
 } while (0)
 
+#define REQUIRE_XMIPSLSP(ctx) do {               \
+    if (!ctx->cfg_ptr->ext_xmipslsp) {           \
+        return false;                            \
+    }                                            \
+} while (0)
+
 static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
 {
     REQUIRE_XMIPSCMOV(ctx);
@@ -47,6 +53,84 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
     return true;
 }
 
+static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
+{
+    REQUIRE_XMIPSLSP(ctx);
+    REQUIRE_64_OR_128BIT(ctx);
+
+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv dest0 = dest_gpr(ctx, a->rd);
+    TCGv dest1 = dest_gpr(ctx, a->rs3);
+    TCGv addr = tcg_temp_new();
+
+    tcg_gen_addi_tl(addr, src, a->imm_y);
+    tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
+    gen_set_gpr(ctx, a->rd, dest0);
+
+    tcg_gen_addi_tl(addr, addr, 8);
+    tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
+    gen_set_gpr(ctx, a->rs3, dest1);
+
+    return true;
+}
+
+static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
+{
+    REQUIRE_XMIPSLSP(ctx);
+
+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv dest0 = dest_gpr(ctx, a->rd);
+    TCGv dest1 = dest_gpr(ctx, a->rs3);
+    TCGv addr = tcg_temp_new();
+
+    tcg_gen_addi_tl(addr, src, a->imm_x);
+    tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
+    gen_set_gpr(ctx, a->rd, dest0);
+
+    tcg_gen_addi_tl(addr, addr, 4);
+    tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
+    gen_set_gpr(ctx, a->rs3, dest1);
+
+    return true;
+}
+
+static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
+{
+    REQUIRE_XMIPSLSP(ctx);
+    REQUIRE_64_OR_128BIT(ctx);
+
+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv data0 = get_gpr(ctx, a->rs2, EXT_NONE);
+    TCGv data1 = get_gpr(ctx, a->rs3, EXT_NONE);
+    TCGv addr = tcg_temp_new();
+
+    tcg_gen_addi_tl(addr, src, a->imm_w);
+    tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
+
+    tcg_gen_addi_tl(addr, addr, 8);
+    tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
+
+    return true;
+}
+
+static bool trans_swp(DisasContext *ctx, arg_swp *a)
+{
+    REQUIRE_XMIPSLSP(ctx);
+
+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv data0 = get_gpr(ctx, a->rs2, EXT_NONE);
+    TCGv data1 = get_gpr(ctx, a->rs3, EXT_NONE);
+    TCGv addr = tcg_temp_new();
+
+    tcg_gen_addi_tl(addr, src, a->imm_v);
+    tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
+
+    tcg_gen_addi_tl(addr, addr, 4);
+    tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
+
+    return true;
+}
+
 static bool trans_pref(DisasContext *ctx, arg_pref *a)
 {
     REQUIRE_XMIPSCBOP(ctx);
diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
index 697bf26c26..99c98d4084 100644
--- a/target/riscv/xmips.decode
+++ b/target/riscv/xmips.decode
@@ -8,5 +8,28 @@
 # Reference: MIPS P8700 instructions
 #            (https://mips.com/products/hardware/p8700/)
 
+# Fields
+%rs3       27:5
+%rs2       20:5
+%rs1       15:5
+%rd        7:5
+%imm_9     20:9
+%imm_hint  7:5
+%imm_v     25:2 9:3               !function=ex_shift_2
+%imm_w     25:2 10:2              !function=ex_shift_3
+%imm_x     22:5                   !function=ex_shift_2
+%imm_y     23:4                   !function=ex_shift_3
+
+# Formats
+@r4_immv ..... .. ..... ..... ... ... .. ....... %rs2 %rs3 %imm_v %rs1
+@r4_immw ..... .. ..... ..... ... .. ... ....... %rs2 %rs3 %imm_w %rs1
+@r4_immx ..... .....  .. ..... ... ..... ....... %rs3 %imm_x %rs1 %rd
+@r4_immy ..... ....  ... ..... ... ..... ....... %rs3 %imm_y %rs1 %rd
+
+# *** RV64 MIPS Extension ***
 ccmov          rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
 pref        000 imm_9:9 rs1:5 000 imm_hint:5 0001011
+ldp         ..... .... 000 ..... 100 .....  0001011 @r4_immy
+lwp         ..... ..... 01 ..... 100 .....  0001011 @r4_immx
+sdp         ..... .. ..... ..... 101 ..  0000001011 @r4_immw
+swp         ..... .. ..... ..... 101 ...  010001011 @r4_immv
-- 
2.34.1
Re: [PATCH v4 07/11] target/riscv: Add Xmipslsp instructions
Posted by Daniel Henrique Barboza 4 months, 2 weeks ago 

On 6/25/25 11:18 AM, Djordje Todorovic wrote:
> Add MIPS P8700 ldp, lwp, sdp, swp instructions.
> 
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---

Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c                        |  3 +
>   target/riscv/cpu_cfg.h                    |  3 +-
>   target/riscv/cpu_cfg_fields.h.inc         |  1 +
>   target/riscv/insn_trans/trans_xmips.c.inc | 84 +++++++++++++++++++++++
>   target/riscv/xmips.decode                 | 23 +++++++
>   5 files changed, 112 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e5194fd06..6e3514a713 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -232,6 +232,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
>       ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop),
>       ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
> +    ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp),
>       ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>       ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
>       ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -1364,6 +1365,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>       MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
>       MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
>       MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
> +    MULTI_EXT_CFG_BOOL("xmipslsp", ext_xmipslsp, false),
>   
>       { },
>   };
> @@ -3182,6 +3184,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.pmp = true,
>           .cfg.ext_zba = true,
>           .cfg.ext_zbb = true,
> +        .cfg.ext_xmipslsp = true,
>           .cfg.ext_xmipscbop = true,
>           .cfg.ext_xmipscmov = true,
>           .cfg.marchid = 0x8000000000000201,
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 9734963035..cd1cba797c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -22,7 +22,6 @@
>   #define RISCV_CPU_CFG_H
>   
>   struct RISCVCPUConfig {
> -
>   #define BOOL_FIELD(x) bool x;
>   #define TYPED_FIELD(type, x, default) type x;
>   #include "cpu_cfg_fields.h.inc"
> @@ -39,7 +38,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
>   
>   static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
>   {
> -    return cfg->ext_xmipscbop || cfg->ext_xmipscmov;
> +    return cfg->ext_xmipscbop || cfg->ext_xmipscmov || cfg->ext_xmipslsp;
>   }
>   
>   static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 9ee0a099bb..b5195959b2 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -147,6 +147,7 @@ BOOL_FIELD(ext_xtheadsync)
>   BOOL_FIELD(ext_XVentanaCondOps)
>   BOOL_FIELD(ext_xmipscbop)
>   BOOL_FIELD(ext_xmipscmov)
> +BOOL_FIELD(ext_xmipslsp)
>   
>   BOOL_FIELD(mmu)
>   BOOL_FIELD(pmp)
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> index 6555a6062a..d2720a6770 100644
> --- a/target/riscv/insn_trans/trans_xmips.c.inc
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -31,6 +31,12 @@
>       }                                            \
>   } while (0)
>   
> +#define REQUIRE_XMIPSLSP(ctx) do {               \
> +    if (!ctx->cfg_ptr->ext_xmipslsp) {           \
> +        return false;                            \
> +    }                                            \
> +} while (0)
> +
>   static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
>   {
>       REQUIRE_XMIPSCMOV(ctx);
> @@ -47,6 +53,84 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
>       return true;
>   }
>   
> +static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
> +{
> +    REQUIRE_XMIPSLSP(ctx);
> +    REQUIRE_64_OR_128BIT(ctx);
> +
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv dest0 = dest_gpr(ctx, a->rd);
> +    TCGv dest1 = dest_gpr(ctx, a->rs3);
> +    TCGv addr = tcg_temp_new();
> +
> +    tcg_gen_addi_tl(addr, src, a->imm_y);
> +    tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
> +    gen_set_gpr(ctx, a->rd, dest0);
> +
> +    tcg_gen_addi_tl(addr, addr, 8);
> +    tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
> +    gen_set_gpr(ctx, a->rs3, dest1);
> +
> +    return true;
> +}
> +
> +static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
> +{
> +    REQUIRE_XMIPSLSP(ctx);
> +
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv dest0 = dest_gpr(ctx, a->rd);
> +    TCGv dest1 = dest_gpr(ctx, a->rs3);
> +    TCGv addr = tcg_temp_new();
> +
> +    tcg_gen_addi_tl(addr, src, a->imm_x);
> +    tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
> +    gen_set_gpr(ctx, a->rd, dest0);
> +
> +    tcg_gen_addi_tl(addr, addr, 4);
> +    tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
> +    gen_set_gpr(ctx, a->rs3, dest1);
> +
> +    return true;
> +}
> +
> +static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
> +{
> +    REQUIRE_XMIPSLSP(ctx);
> +    REQUIRE_64_OR_128BIT(ctx);
> +
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv data0 = get_gpr(ctx, a->rs2, EXT_NONE);
> +    TCGv data1 = get_gpr(ctx, a->rs3, EXT_NONE);
> +    TCGv addr = tcg_temp_new();
> +
> +    tcg_gen_addi_tl(addr, src, a->imm_w);
> +    tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
> +
> +    tcg_gen_addi_tl(addr, addr, 8);
> +    tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
> +
> +    return true;
> +}
> +
> +static bool trans_swp(DisasContext *ctx, arg_swp *a)
> +{
> +    REQUIRE_XMIPSLSP(ctx);
> +
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv data0 = get_gpr(ctx, a->rs2, EXT_NONE);
> +    TCGv data1 = get_gpr(ctx, a->rs3, EXT_NONE);
> +    TCGv addr = tcg_temp_new();
> +
> +    tcg_gen_addi_tl(addr, src, a->imm_v);
> +    tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
> +
> +    tcg_gen_addi_tl(addr, addr, 4);
> +    tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
> +
> +    return true;
> +}
> +
>   static bool trans_pref(DisasContext *ctx, arg_pref *a)
>   {
>       REQUIRE_XMIPSCBOP(ctx);
> diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
> index 697bf26c26..99c98d4084 100644
> --- a/target/riscv/xmips.decode
> +++ b/target/riscv/xmips.decode
> @@ -8,5 +8,28 @@
>   # Reference: MIPS P8700 instructions
>   #            (https://mips.com/products/hardware/p8700/)
>   
> +# Fields
> +%rs3       27:5
> +%rs2       20:5
> +%rs1       15:5
> +%rd        7:5
> +%imm_9     20:9
> +%imm_hint  7:5
> +%imm_v     25:2 9:3               !function=ex_shift_2
> +%imm_w     25:2 10:2              !function=ex_shift_3
> +%imm_x     22:5                   !function=ex_shift_2
> +%imm_y     23:4                   !function=ex_shift_3
> +
> +# Formats
> +@r4_immv ..... .. ..... ..... ... ... .. ....... %rs2 %rs3 %imm_v %rs1
> +@r4_immw ..... .. ..... ..... ... .. ... ....... %rs2 %rs3 %imm_w %rs1
> +@r4_immx ..... .....  .. ..... ... ..... ....... %rs3 %imm_x %rs1 %rd
> +@r4_immy ..... ....  ... ..... ... ..... ....... %rs3 %imm_y %rs1 %rd
> +
> +# *** RV64 MIPS Extension ***
>   ccmov          rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
>   pref        000 imm_9:9 rs1:5 000 imm_hint:5 0001011
> +ldp         ..... .... 000 ..... 100 .....  0001011 @r4_immy
> +lwp         ..... ..... 01 ..... 100 .....  0001011 @r4_immx
> +sdp         ..... .. ..... ..... 101 ..  0000001011 @r4_immw
> +swp         ..... .. ..... ..... 101 ...  010001011 @r4_immv

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