On 6/25/25 11:18 AM, Djordje Todorovic wrote:
> Add MIPS P8700 prefetch instruction defined by Xmipscbop.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 3 +++
> target/riscv/cpu_cfg.h | 3 ++-
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/insn_trans/trans_xmips.c.inc | 14 ++++++++++++++
> target/riscv/xmips.decode | 1 +
> 5 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d48fd4df4e..1e5194fd06 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -230,6 +230,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> + ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop),
> ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> @@ -1361,6 +1362,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
> MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
> MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
> + MULTI_EXT_CFG_BOOL("xmipscbop", ext_xmipscbop, false),
> MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
>
> { },
> @@ -3180,6 +3182,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.pmp = true,
> .cfg.ext_zba = true,
> .cfg.ext_zbb = true,
> + .cfg.ext_xmipscbop = true,
> .cfg.ext_xmipscmov = true,
> .cfg.marchid = 0x8000000000000201,
> .cfg.mvendorid = MIPS_VENDOR_ID,
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 2db471ad17..9734963035 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -22,6 +22,7 @@
> #define RISCV_CPU_CFG_H
>
> struct RISCVCPUConfig {
> +
> #define BOOL_FIELD(x) bool x;
> #define TYPED_FIELD(type, x, default) type x;
> #include "cpu_cfg_fields.h.inc"
> @@ -38,7 +39,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
>
> static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
> {
> - return cfg->ext_xmipscmov;
> + return cfg->ext_xmipscbop || cfg->ext_xmipscmov;
> }
>
> static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index baedf0c466..9ee0a099bb 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -145,6 +145,7 @@ BOOL_FIELD(ext_xtheadmemidx)
> BOOL_FIELD(ext_xtheadmempair)
> BOOL_FIELD(ext_xtheadsync)
> BOOL_FIELD(ext_XVentanaCondOps)
> +BOOL_FIELD(ext_xmipscbop)
> BOOL_FIELD(ext_xmipscmov)
>
> BOOL_FIELD(mmu)
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> index 269b1082a6..6555a6062a 100644
> --- a/target/riscv/insn_trans/trans_xmips.c.inc
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -19,6 +19,12 @@
> * (https://mips.com/products/hardware/p8700/)
> */
>
> +#define REQUIRE_XMIPSCBOP(ctx) do { \
> + if (!ctx->cfg_ptr->ext_xmipscbop) { \
> + return false; \
> + } \
> +} while (0)
> +
> #define REQUIRE_XMIPSCMOV(ctx) do { \
> if (!ctx->cfg_ptr->ext_xmipscmov) { \
> return false; \
> @@ -40,3 +46,11 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
>
> return true;
> }
> +
> +static bool trans_pref(DisasContext *ctx, arg_pref *a)
> +{
> + REQUIRE_XMIPSCBOP(ctx);
> +
> + /* Nop */
> + return true;
> +}
> diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
> index cb334fa4bd..697bf26c26 100644
> --- a/target/riscv/xmips.decode
> +++ b/target/riscv/xmips.decode
> @@ -9,3 +9,4 @@
> # (https://mips.com/products/hardware/p8700/)
>
> ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
> +pref 000 imm_9:9 rs1:5 000 imm_hint:5 0001011