riscv: add all available CSRs to 'info registers'

[PATCH 2/3] target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()

Posted by Daniel Henrique Barboza 7 months, 2 weeks ago

We're missing fflags and frm.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 67e4eda4f9..95d0b88937 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -593,6 +593,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         }
     }
     if (flags & CPU_DUMP_FPU) {
+        riscv_dump_csr(env, CSR_FFLAGS, f);
+        riscv_dump_csr(env, CSR_FRM, f);
         riscv_dump_csr(env, CSR_FCSR, f);
 
         for (i = 0; i < 32; i++) {
-- 
2.49.0

Re: [PATCH 2/3] target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()

Posted by Alistair Francis 4 months, 3 weeks ago

On Tue, Jun 24, 2025 at 3:22 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We're missing fflags and frm.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 67e4eda4f9..95d0b88937 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -593,6 +593,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>          }
>      }
>      if (flags & CPU_DUMP_FPU) {
> +        riscv_dump_csr(env, CSR_FFLAGS, f);
> +        riscv_dump_csr(env, CSR_FRM, f);
>          riscv_dump_csr(env, CSR_FCSR, f);
>
>          for (i = 0; i < 32; i++) {
> --
> 2.49.0
>
>

[PATCH 1/3] target/riscv/cpu: add riscv_dump_csr() helper
[PATCH 2/3] target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
[PATCH 3/3] target/riscv: print all available CSRs in riscv_cpu_dump_state()