riscv: add all available CSRs to 'info registers'

[PATCH 1/3] target/riscv/cpu: add riscv_dump_csr() helper

Posted by Daniel Henrique Barboza 7 months, 2 weeks ago

riscv_cpu_dump_state() is using the same pattern to print a CSR given
its number. Add a helper to avoid code repetition.

While we're at it fix the identation of the 'flags & CPU_DUMP_VPU'
block.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 54 +++++++++++++++++++---------------------------
 1 file changed, 22 insertions(+), 32 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e3f8ecef68..67e4eda4f9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -515,6 +515,21 @@ char *riscv_cpu_get_name(RISCVCPU *cpu)
     return cpu_model_from_type(typename);
 }
 
+static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
+{
+    target_ulong val = 0;
+    RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+    /*
+     * Rely on the smode, hmode, etc, predicates within csr.c
+     * to do the filtering of the registers that are present.
+     */
+    if (res == RISCV_EXCP_NONE) {
+        qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                     csr_ops[csrno].name, val);
+    }
+}
+
 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
@@ -565,18 +580,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         };
 
         for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
-            int csrno = dump_csrs[i];
-            target_ulong val = 0;
-            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
-
-            /*
-             * Rely on the smode, hmode, etc, predicates within csr.c
-             * to do the filtering of the registers that are present.
-             */
-            if (res == RISCV_EXCP_NONE) {
-                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
-                             csr_ops[csrno].name, val);
-            }
+            riscv_dump_csr(env, dump_csrs[i], f);
         }
     }
 #endif
@@ -589,12 +593,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         }
     }
     if (flags & CPU_DUMP_FPU) {
-        target_ulong val = 0;
-        RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
-        if (res == RISCV_EXCP_NONE) {
-            qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
-                    csr_ops[CSR_FCSR].name, val);
-        }
+        riscv_dump_csr(env, CSR_FCSR, f);
+
         for (i = 0; i < 32; i++) {
             qemu_fprintf(f, " %-8s %016" PRIx64,
                          riscv_fpr_regnames[i], env->fpr[i]);
@@ -612,22 +612,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                     CSR_VL,
                     CSR_VTYPE,
                     CSR_VLENB,
-                };
-        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
-            int csrno = dump_rvv_csrs[i];
-            target_ulong val = 0;
-            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+        };
+        uint16_t vlenb = cpu->cfg.vlenb;
 
-            /*
-             * Rely on the smode, hmode, etc, predicates within csr.c
-             * to do the filtering of the registers that are present.
-             */
-            if (res == RISCV_EXCP_NONE) {
-                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
-                             csr_ops[csrno].name, val);
-            }
+        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+            riscv_dump_csr(env, dump_rvv_csrs[i], f);
         }
-        uint16_t vlenb = cpu->cfg.vlenb;
 
         for (i = 0; i < 32; i++) {
             qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
-- 
2.49.0

Re: [PATCH 1/3] target/riscv/cpu: add riscv_dump_csr() helper

Posted by Alistair Francis 4 months, 3 weeks ago

On Tue, Jun 24, 2025 at 3:22 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> riscv_cpu_dump_state() is using the same pattern to print a CSR given
> its number. Add a helper to avoid code repetition.
>
> While we're at it fix the identation of the 'flags & CPU_DUMP_VPU'
> block.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 54 +++++++++++++++++++---------------------------
>  1 file changed, 22 insertions(+), 32 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e3f8ecef68..67e4eda4f9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -515,6 +515,21 @@ char *riscv_cpu_get_name(RISCVCPU *cpu)
>      return cpu_model_from_type(typename);
>  }
>
> +static void riscv_dump_csr(CPURISCVState *env, int csrno, FILE *f)
> +{
> +    target_ulong val = 0;
> +    RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> +    /*
> +     * Rely on the smode, hmode, etc, predicates within csr.c
> +     * to do the filtering of the registers that are present.
> +     */
> +    if (res == RISCV_EXCP_NONE) {
> +        qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> +                     csr_ops[csrno].name, val);
> +    }
> +}
> +
>  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
> @@ -565,18 +580,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>          };
>
>          for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> -            int csrno = dump_csrs[i];
> -            target_ulong val = 0;
> -            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> -
> -            /*
> -             * Rely on the smode, hmode, etc, predicates within csr.c
> -             * to do the filtering of the registers that are present.
> -             */
> -            if (res == RISCV_EXCP_NONE) {
> -                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> -                             csr_ops[csrno].name, val);
> -            }
> +            riscv_dump_csr(env, dump_csrs[i], f);
>          }
>      }
>  #endif
> @@ -589,12 +593,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>          }
>      }
>      if (flags & CPU_DUMP_FPU) {
> -        target_ulong val = 0;
> -        RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
> -        if (res == RISCV_EXCP_NONE) {
> -            qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> -                    csr_ops[CSR_FCSR].name, val);
> -        }
> +        riscv_dump_csr(env, CSR_FCSR, f);
> +
>          for (i = 0; i < 32; i++) {
>              qemu_fprintf(f, " %-8s %016" PRIx64,
>                           riscv_fpr_regnames[i], env->fpr[i]);
> @@ -612,22 +612,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>                      CSR_VL,
>                      CSR_VTYPE,
>                      CSR_VLENB,
> -                };
> -        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> -            int csrno = dump_rvv_csrs[i];
> -            target_ulong val = 0;
> -            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +        };
> +        uint16_t vlenb = cpu->cfg.vlenb;
>
> -            /*
> -             * Rely on the smode, hmode, etc, predicates within csr.c
> -             * to do the filtering of the registers that are present.
> -             */
> -            if (res == RISCV_EXCP_NONE) {
> -                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> -                             csr_ops[csrno].name, val);
> -            }
> +        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> +            riscv_dump_csr(env, dump_rvv_csrs[i], f);
>          }
> -        uint16_t vlenb = cpu->cfg.vlenb;
>
>          for (i = 0; i < 32; i++) {
>              qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
> --
> 2.49.0
>
>

[PATCH 1/3] target/riscv/cpu: add riscv_dump_csr() helper
[PATCH 2/3] target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
[PATCH 3/3] target/riscv: print all available CSRs in riscv_cpu_dump_state()