riscv: add all available CSRs to 'info registers'

[PATCH 0/3] riscv: add all available CSRs to 'info registers'

Posted by Daniel Henrique Barboza 7 months, 2 weeks ago

Hi,

The output of HMP 'info registers', implemented by the cpu_dump_state
callback, returns way less CSRs than what we have available in the
default rv64 CPU with default options. 

This series changes the callback to add all available non-vector CSRs
when issuing 'info registers'. The vector CSRs are being handled by
another patch [1]. 

Patches based on alistair/riscv-to-apply.next.

[1] https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarboza@ventanamicro.com/


Daniel Henrique Barboza (3):
  target/riscv/cpu: add riscv_dump_csr() helper
  target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
  target/riscv: print all available CSRs in riscv_cpu_dump_state()

 target/riscv/cpu.c | 107 +++++++++++++++++----------------------------
 target/riscv/cpu.h |   2 +
 target/riscv/csr.c |  18 ++++++++
 3 files changed, 61 insertions(+), 66 deletions(-)

-- 
2.49.0

Re: [PATCH 0/3] riscv: add all available CSRs to 'info registers'

Posted by Daniel Henrique Barboza 5 months ago

Ping

On 6/23/25 2:21 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> The output of HMP 'info registers', implemented by the cpu_dump_state
> callback, returns way less CSRs than what we have available in the
> default rv64 CPU with default options.
> 
> This series changes the callback to add all available non-vector CSRs
> when issuing 'info registers'. The vector CSRs are being handled by
> another patch [1].
> 
> Patches based on alistair/riscv-to-apply.next.
> 
> [1] https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarboza@ventanamicro.com/
> 
> 
> Daniel Henrique Barboza (3):
>    target/riscv/cpu: add riscv_dump_csr() helper
>    target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
>    target/riscv: print all available CSRs in riscv_cpu_dump_state()
> 
>   target/riscv/cpu.c | 107 +++++++++++++++++----------------------------
>   target/riscv/cpu.h |   2 +
>   target/riscv/csr.c |  18 ++++++++
>   3 files changed, 61 insertions(+), 66 deletions(-)
>

Re: [PATCH 0/3] riscv: add all available CSRs to 'info registers'

Posted by Anton Johansson via 5 months ago

On 23/06/25, Daniel Henrique Barboza wrote:
> Hi,
> 
> The output of HMP 'info registers', implemented by the cpu_dump_state
> callback, returns way less CSRs than what we have available in the
> default rv64 CPU with default options. 
> 
> This series changes the callback to add all available non-vector CSRs
> when issuing 'info registers'. The vector CSRs are being handled by
> another patch [1]. 
> 
> Patches based on alistair/riscv-to-apply.next.
> 
> [1] https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarboza@ventanamicro.com/
> 
> 
> Daniel Henrique Barboza (3):
>   target/riscv/cpu: add riscv_dump_csr() helper
>   target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
>   target/riscv: print all available CSRs in riscv_cpu_dump_state()
> 
>  target/riscv/cpu.c | 107 +++++++++++++++++----------------------------
>  target/riscv/cpu.h |   2 +
>  target/riscv/csr.c |  18 ++++++++
>  3 files changed, 61 insertions(+), 66 deletions(-)
> 
> -- 
> 2.49.0
> 
> 

I think this makes sense, less manual maintainence is always a plus!:)

Series: reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH 0/3] riscv: add all available CSRs to 'info registers'

Posted by Alistair Francis 3 months, 1 week ago

On Tue, Jun 24, 2025 at 3:22 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> The output of HMP 'info registers', implemented by the cpu_dump_state
> callback, returns way less CSRs than what we have available in the
> default rv64 CPU with default options.
>
> This series changes the callback to add all available non-vector CSRs
> when issuing 'info registers'. The vector CSRs are being handled by
> another patch [1].
>
> Patches based on alistair/riscv-to-apply.next.
>
> [1] https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarboza@ventanamicro.com/
>
>
> Daniel Henrique Barboza (3):
>   target/riscv/cpu: add riscv_dump_csr() helper
>   target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
>   target/riscv: print all available CSRs in riscv_cpu_dump_state()

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c | 107 +++++++++++++++++----------------------------
>  target/riscv/cpu.h |   2 +
>  target/riscv/csr.c |  18 ++++++++
>  3 files changed, 61 insertions(+), 66 deletions(-)
>
> --
> 2.49.0
>
>

Re: [PATCH 0/3] riscv: add all available CSRs to 'info registers'

Posted by Daniel Henrique Barboza 7 months ago

Ping

It would be nice to have all CSRs for 'info registers' for the next release.
We have one week before the freeze :D


Thanks,

Daniel

On 6/23/25 2:21 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> The output of HMP 'info registers', implemented by the cpu_dump_state
> callback, returns way less CSRs than what we have available in the
> default rv64 CPU with default options.
> 
> This series changes the callback to add all available non-vector CSRs
> when issuing 'info registers'. The vector CSRs are being handled by
> another patch [1].
> 
> Patches based on alistair/riscv-to-apply.next.
> 
> [1] https://lore.kernel.org/qemu-riscv/20250623145306.991562-1-dbarboza@ventanamicro.com/
> 
> 
> Daniel Henrique Barboza (3):
>    target/riscv/cpu: add riscv_dump_csr() helper
>    target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
>    target/riscv: print all available CSRs in riscv_cpu_dump_state()
> 
>   target/riscv/cpu.c | 107 +++++++++++++++++----------------------------
>   target/riscv/cpu.h |   2 +
>   target/riscv/csr.c |  18 ++++++++
>   3 files changed, 61 insertions(+), 66 deletions(-)
>