Tracing an Apple M1 (Icestorm core, ARMv8.4-A):
hvf_processor_feature_register EL0: 1
hvf_processor_feature_register EL1: 1
hvf_processor_feature_register EL2: 0
hvf_processor_feature_register FP: 1
hvf_processor_feature_register AdvSIMD: 1
hvf_processor_feature_register GIC: 0
hvf_processor_feature_register SVE: 0
hvf_processor_feature_register MTE: 0
hvf_processor_feature_register SME: 0
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/hvf/hvf.c | 43 +++++++++++++++++++++++++++++++++++++
target/arm/hvf/trace-events | 1 +
2 files changed, 44 insertions(+)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 52199c4ff9d..87cd323c14d 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -2160,8 +2160,51 @@ static void hvf_vm_state_change(void *opaque, bool running, RunState state)
}
}
+static void trace_processor_feature_register(void)
+{
+ hv_return_t ret = HV_SUCCESS;
+ hv_vcpu_exit_t *exit;
+ hv_vcpu_t fd;
+ uint64_t pfr;
+
+ if (!trace_event_get_state_backends(TRACE_HVF_PROCESSOR_FEATURE_REGISTER)) {
+ return;
+ }
+
+ /* We set up a small vcpu to extract host registers */
+ ret = hv_vcpu_create(&fd, &exit, NULL);
+ assert_hvf_ok(ret);
+
+ ret = hv_vcpu_get_sys_reg(fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
+ assert_hvf_ok(ret);
+ trace_hvf_processor_feature_register("EL0",
+ FIELD_EX64(pfr, ID_AA64PFR0, EL0));
+ trace_hvf_processor_feature_register("EL1",
+ FIELD_EX64(pfr, ID_AA64PFR0, EL1));
+ trace_hvf_processor_feature_register("EL2",
+ FIELD_EX64(pfr, ID_AA64PFR0, EL2));
+ trace_hvf_processor_feature_register("FP",
+ FIELD_EX64(pfr, ID_AA64PFR0, FP));
+ trace_hvf_processor_feature_register("AdvSIMD", FIELD_EX64(pfr,
+ ID_AA64PFR0, ADVSIMD));
+ trace_hvf_processor_feature_register("GIC", FIELD_EX64(pfr,
+ ID_AA64PFR0, GIC));
+ trace_hvf_processor_feature_register("SVE", FIELD_EX64(pfr,
+ ID_AA64PFR0, SVE));
+
+ ret = hv_vcpu_get_sys_reg(fd, HV_SYS_REG_ID_AA64PFR1_EL1, &pfr);
+ assert_hvf_ok(ret);
+ trace_hvf_processor_feature_register("MTE",
+ FIELD_EX64(pfr, ID_AA64PFR1, MTE));
+ trace_hvf_processor_feature_register("SME",
+ FIELD_EX64(pfr, ID_AA64PFR1, SME));
+ ret = hv_vcpu_destroy(fd);
+ assert_hvf_ok(ret);
+}
+
int hvf_arch_init(void)
{
+ trace_processor_feature_register();
hvf_state->vtimer_offset = mach_absolute_time();
vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer);
qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
index b49746f28d1..7ef75184901 100644
--- a/target/arm/hvf/trace-events
+++ b/target/arm/hvf/trace-events
@@ -12,3 +12,4 @@ hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid
hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
hvf_illegal_guest_state(void) "HV_ILLEGAL_GUEST_STATE"
+hvf_processor_feature_register(const char *regname, unsigned value) "%s: %u"
--
2.49.0