On 2025/6/19 上午10:39, Song Gao wrote:
> Implement avec set irq and update CSR_MSIS and CSR_MSGIR.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/intc/loongarch_avec.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c
> index 7dd8bac696..bbd1b48c7d 100644
> --- a/hw/intc/loongarch_avec.c
> +++ b/hw/intc/loongarch_avec.c
> @@ -16,6 +16,12 @@
> #include "migration/vmstate.h"
> #include "trace.h"
> #include "hw/qdev-properties.h"
> +#include "target/loongarch/cpu.h"
> +
> +/* msg addr field */
> +FIELD(MSG_ADDR, IRQ_NUM, 4, 8)
> +FIELD(MSG_ADDR, CPU_NUM, 12, 8)
> +FIELD(MSG_ADDR, FIX, 28, 12)
>
> static uint64_t loongarch_avec_mem_read(void *opaque,
> hwaddr addr, unsigned size)
> @@ -23,12 +29,33 @@ static uint64_t loongarch_avec_mem_read(void *opaque,
> return 0;
> }
>
> +static void avec_set_irq(LoongArchAVECState *s, int cpu_num, int irq_num, int level)
> +{
> + MachineState *machine = MACHINE(qdev_get_machine());
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> + const CPUArchIdList *id_list = NULL;
> + assert(mc->possible_cpu_arch_ids(machine));
> + id_list = mc->possible_cpu_arch_ids(machine);
> + CPUState *cpu = id_list->cpus[cpu_num].cpu;
> + CPULoongArchState *env = &LOONGARCH_CPU(cpu)->env;
> +
> + set_bit(irq_num, &env->CSR_MSGIS[irq_num / 64]);
> + qemu_set_irq(s->cpu[cpu_num].parent_irq, 1);
> + env->CSR_MSGIR = FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, INTNUM, irq_num);
> + env->CSR_MSGIR = FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 0);
I think that CSR_MSGIR should be set in this function. CSR_MSGIR is read
only logic register, it get and clear nearest bit about CSR_MSGIS[4] in
CSR register emulation.
And when all bits about CSR_MSGIS[4] are cleared, parent irq can be set
with 0 such as:
qemu_set_irq(s->cpu[cpu_num].parent_irq, 0);
Regards
Bibo Mao
> +}
> +
> static void loongarch_avec_mem_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> - return;
> -}
> + int irq_num, cpu_num = 0;
> + LoongArchAVECState *s = LOONGARCH_AVEC(opaque);
> + uint64_t msg_addr = addr + VIRT_AVEC_BASE;
>
> + cpu_num = FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM);
> + irq_num = FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM);
> + avec_set_irq(s, cpu_num, irq_num, 1);
> +}
>
> static const MemoryRegionOps loongarch_avec_ops = {
> .read = loongarch_avec_mem_read,
>