Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 12 +++
target/riscv/meson.build | 1 +
target/riscv/mips_csr.c | 219 +++++++++++++++++++++++++++++++++++++++
4 files changed, 235 insertions(+)
create mode 100644 target/riscv/mips_csr.c
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index be362e1644..1e85a16971 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3179,6 +3179,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_zba = true,
.cfg.ext_zbb = true,
.cfg.marchid = 0x8000000000000201,
+#ifndef CONFIG_USER_ONLY
+ .custom_csrs = mips_csr_list,
+#endif
),
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fba0b0506b..bf1a931e60 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -199,6 +199,13 @@ typedef struct PMUFixedCtrState {
uint64_t counter_virt_prev[2];
} PMUFixedCtrState;
+struct MIPSCSR {
+ uint64_t tvec;
+ uint64_t config[12];
+ uint64_t pmacfg[15];
+};
+typedef struct MIPSCSR MIPSCSR;
+
struct CPUArchState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
@@ -497,6 +504,8 @@ struct CPUArchState {
target_ulong rnmip;
uint64_t rnmi_irqvec;
uint64_t rnmi_excpvec;
+
+ MIPSCSR mips_csrs;
};
/*
@@ -972,5 +981,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
/* In th_csr.c */
extern const RISCVCSR th_csr_list[];
+/* Implemented in mips_csr.c */
+extern const RISCVCSR mips_csr_list[];
+
const char *priv_spec_to_str(int priv_version);
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a4bd61e52a..fbb6c8fb45 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -32,6 +32,7 @@ riscv_system_ss.add(files(
'debug.c',
'monitor.c',
'machine.c',
+ 'mips_csr.c',
'pmu.c',
'th_csr.c',
'time_helper.c',
diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c
new file mode 100644
index 0000000000..aab7f832a0
--- /dev/null
+++ b/target/riscv/mips_csr.c
@@ -0,0 +1,219 @@
+/*
+ * MIPS-specific CSRs.
+ *
+ * Copyright (c) 2025 MIPS
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+/* MIPS CSR */
+#define CSR_MIPSTVEC 0x7c0
+#define CSR_MIPSCONFIG0 0x7d0
+#define CSR_MIPSCONFIG1 0x7d1
+#define CSR_MIPSCONFIG2 0x7d2
+#define CSR_MIPSCONFIG3 0x7d3
+#define CSR_MIPSCONFIG4 0x7d4
+#define CSR_MIPSCONFIG5 0x7d5
+#define CSR_MIPSCONFIG6 0x7d6
+#define CSR_MIPSCONFIG7 0x7d7
+#define CSR_MIPSCONFIG8 0x7d8
+#define CSR_MIPSCONFIG9 0x7d9
+#define CSR_MIPSCONFIG10 0x7da
+#define CSR_MIPSCONFIG11 0x7db
+#define CSR_MIPSPMACFG0 0x7e0
+#define CSR_MIPSPMACFG1 0x7e1
+#define CSR_MIPSPMACFG2 0x7e2
+#define CSR_MIPSPMACFG3 0x7e3
+#define CSR_MIPSPMACFG4 0x7e4
+#define CSR_MIPSPMACFG5 0x7e5
+#define CSR_MIPSPMACFG6 0x7e6
+#define CSR_MIPSPMACFG7 0x7e7
+#define CSR_MIPSPMACFG8 0x7e8
+#define CSR_MIPSPMACFG9 0x7e9
+#define CSR_MIPSPMACFG10 0x7ea
+#define CSR_MIPSPMACFG11 0x7eb
+#define CSR_MIPSPMACFG12 0x7ec
+#define CSR_MIPSPMACFG13 0x7ed
+#define CSR_MIPSPMACFG14 0x7ee
+#define CSR_MIPSPMACFG15 0x7ef
+
+static RISCVException any(CPURISCVState *env, int csrno)
+{
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipstvec(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->mips_csrs.tvec;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mipstvec(CPURISCVState *env, int csrno,
+ target_ulong val, uintptr_t ra)
+{
+ env->mips_csrs.tvec = val;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipsconfig(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->mips_csrs.config[csrno - CSR_MIPSCONFIG0];
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mipsconfig(CPURISCVState *env, int csrno,
+ target_ulong val, uintptr_t ra)
+{
+ env->mips_csrs.config[csrno - CSR_MIPSCONFIG0] = val;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0];
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno,
+ target_ulong val, uintptr_t ra)
+{
+ env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0] = val;
+ return RISCV_EXCP_NONE;
+}
+
+const RISCVCSR mips_csr_list[] = {
+ {
+ .csrno = CSR_MIPSTVEC,
+ .csr_ops = { "mipstvec", any, read_mipstvec, write_mipstvec }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG0,
+ .csr_ops = { "mipsconfig0", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG1,
+ .csr_ops = { "mipsconfig1", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG2,
+ .csr_ops = { "mipsconfig2", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG3,
+ .csr_ops = { "mipsconfig3", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG4,
+ .csr_ops = { "mipsconfig4", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG5,
+ .csr_ops = { "mipsconfig5", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG6,
+ .csr_ops = { "mipsconfig6", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG7,
+ .csr_ops = { "mipsconfig7", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG8,
+ .csr_ops = { "mipsconfig8", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG9,
+ .csr_ops = { "mipsconfig9", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG10,
+ .csr_ops = { "mipsconfig10", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSCONFIG11,
+ .csr_ops = { "mipsconfig11", any, read_mipsconfig, write_mipsconfig }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG0,
+ .csr_ops = { "mipspmacfg0", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG1,
+ .csr_ops = { "mipspmacfg1", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG2,
+ .csr_ops = { "mipspmacfg2", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG3,
+ .csr_ops = { "mipspmacfg3", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG4,
+ .csr_ops = { "mipspmacfg4", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG5,
+ .csr_ops = { "mipspmacfg5", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG6,
+ .csr_ops = { "mipspmacfg6", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG7,
+ .csr_ops = { "mipspmacfg7", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG8,
+ .csr_ops = { "mipspmacfg8", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG9,
+ .csr_ops = { "mipspmacfg9", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG10,
+ .csr_ops = { "mipspmacfg10", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG11,
+ .csr_ops = { "mipspmacfg11", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG12,
+ .csr_ops = { "mipspmacfg12", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG13,
+ .csr_ops = { "mipspmacfg13", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG14,
+ .csr_ops = { "mipspmacfg14", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ {
+ .csrno = CSR_MIPSPMACFG15,
+ .csr_ops = { "mipspmacfg15", any, read_mipspmacfg, write_mipspmacfg }
+ },
+ { },
+};
--
2.34.1
On 6/18/25 9:27 AM, Djordje Todorovic wrote:
> Define MIPS CSRs used for P8700 CPU.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
> target/riscv/cpu.c | 3 +
> target/riscv/cpu.h | 12 +++
> target/riscv/meson.build | 1 +
> target/riscv/mips_csr.c | 219 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 235 insertions(+)
> create mode 100644 target/riscv/mips_csr.c
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index be362e1644..1e85a16971 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3179,6 +3179,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.ext_zba = true,
> .cfg.ext_zbb = true,
> .cfg.marchid = 0x8000000000000201,
> +#ifndef CONFIG_USER_ONLY
> + .custom_csrs = mips_csr_list,
> +#endif
> ),
>
> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fba0b0506b..bf1a931e60 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -199,6 +199,13 @@ typedef struct PMUFixedCtrState {
> uint64_t counter_virt_prev[2];
> } PMUFixedCtrState;
>
> +struct MIPSCSR {
> + uint64_t tvec;
> + uint64_t config[12];
> + uint64_t pmacfg[15];
> +};
> +typedef struct MIPSCSR MIPSCSR;
> +
> struct CPUArchState {
> target_ulong gpr[32];
> target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
> @@ -497,6 +504,8 @@ struct CPUArchState {
> target_ulong rnmip;
> uint64_t rnmi_irqvec;
> uint64_t rnmi_excpvec;
> +
> + MIPSCSR mips_csrs;
I suggest a static MIPSCSR struct inside mips_csr.c so you can read/write the CSRs
locally instead of adding MIPS-only attibutes in the common CPU state.
Thanks,
Daniel
> };
>
> /*
> @@ -972,5 +981,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
> /* In th_csr.c */
> extern const RISCVCSR th_csr_list[];
>
> +/* Implemented in mips_csr.c */
> +extern const RISCVCSR mips_csr_list[];
> +
> const char *priv_spec_to_str(int priv_version);
> #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index a4bd61e52a..fbb6c8fb45 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -32,6 +32,7 @@ riscv_system_ss.add(files(
> 'debug.c',
> 'monitor.c',
> 'machine.c',
> + 'mips_csr.c',
> 'pmu.c',
> 'th_csr.c',
> 'time_helper.c',
> diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c
> new file mode 100644
> index 0000000000..aab7f832a0
> --- /dev/null
> +++ b/target/riscv/mips_csr.c
> @@ -0,0 +1,219 @@
> +/*
> + * MIPS-specific CSRs.
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "cpu_vendorid.h"
> +
> +/* MIPS CSR */
> +#define CSR_MIPSTVEC 0x7c0
> +#define CSR_MIPSCONFIG0 0x7d0
> +#define CSR_MIPSCONFIG1 0x7d1
> +#define CSR_MIPSCONFIG2 0x7d2
> +#define CSR_MIPSCONFIG3 0x7d3
> +#define CSR_MIPSCONFIG4 0x7d4
> +#define CSR_MIPSCONFIG5 0x7d5
> +#define CSR_MIPSCONFIG6 0x7d6
> +#define CSR_MIPSCONFIG7 0x7d7
> +#define CSR_MIPSCONFIG8 0x7d8
> +#define CSR_MIPSCONFIG9 0x7d9
> +#define CSR_MIPSCONFIG10 0x7da
> +#define CSR_MIPSCONFIG11 0x7db
> +#define CSR_MIPSPMACFG0 0x7e0
> +#define CSR_MIPSPMACFG1 0x7e1
> +#define CSR_MIPSPMACFG2 0x7e2
> +#define CSR_MIPSPMACFG3 0x7e3
> +#define CSR_MIPSPMACFG4 0x7e4
> +#define CSR_MIPSPMACFG5 0x7e5
> +#define CSR_MIPSPMACFG6 0x7e6
> +#define CSR_MIPSPMACFG7 0x7e7
> +#define CSR_MIPSPMACFG8 0x7e8
> +#define CSR_MIPSPMACFG9 0x7e9
> +#define CSR_MIPSPMACFG10 0x7ea
> +#define CSR_MIPSPMACFG11 0x7eb
> +#define CSR_MIPSPMACFG12 0x7ec
> +#define CSR_MIPSPMACFG13 0x7ed
> +#define CSR_MIPSPMACFG14 0x7ee
> +#define CSR_MIPSPMACFG15 0x7ef
> +
> +static RISCVException any(CPURISCVState *env, int csrno)
> +{
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipstvec(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + *val = env->mips_csrs.tvec;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_mipstvec(CPURISCVState *env, int csrno,
> + target_ulong val, uintptr_t ra)
> +{
> + env->mips_csrs.tvec = val;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipsconfig(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + *val = env->mips_csrs.config[csrno - CSR_MIPSCONFIG0];
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_mipsconfig(CPURISCVState *env, int csrno,
> + target_ulong val, uintptr_t ra)
> +{
> + env->mips_csrs.config[csrno - CSR_MIPSCONFIG0] = val;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + *val = env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0];
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno,
> + target_ulong val, uintptr_t ra)
> +{
> + env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0] = val;
> + return RISCV_EXCP_NONE;
> +}
> +
> +const RISCVCSR mips_csr_list[] = {
> + {
> + .csrno = CSR_MIPSTVEC,
> + .csr_ops = { "mipstvec", any, read_mipstvec, write_mipstvec }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG0,
> + .csr_ops = { "mipsconfig0", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG1,
> + .csr_ops = { "mipsconfig1", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG2,
> + .csr_ops = { "mipsconfig2", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG3,
> + .csr_ops = { "mipsconfig3", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG4,
> + .csr_ops = { "mipsconfig4", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG5,
> + .csr_ops = { "mipsconfig5", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG6,
> + .csr_ops = { "mipsconfig6", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG7,
> + .csr_ops = { "mipsconfig7", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG8,
> + .csr_ops = { "mipsconfig8", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG9,
> + .csr_ops = { "mipsconfig9", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG10,
> + .csr_ops = { "mipsconfig10", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSCONFIG11,
> + .csr_ops = { "mipsconfig11", any, read_mipsconfig, write_mipsconfig }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG0,
> + .csr_ops = { "mipspmacfg0", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG1,
> + .csr_ops = { "mipspmacfg1", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG2,
> + .csr_ops = { "mipspmacfg2", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG3,
> + .csr_ops = { "mipspmacfg3", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG4,
> + .csr_ops = { "mipspmacfg4", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG5,
> + .csr_ops = { "mipspmacfg5", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG6,
> + .csr_ops = { "mipspmacfg6", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG7,
> + .csr_ops = { "mipspmacfg7", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG8,
> + .csr_ops = { "mipspmacfg8", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG9,
> + .csr_ops = { "mipspmacfg9", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG10,
> + .csr_ops = { "mipspmacfg10", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG11,
> + .csr_ops = { "mipspmacfg11", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG12,
> + .csr_ops = { "mipspmacfg12", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG13,
> + .csr_ops = { "mipspmacfg13", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG14,
> + .csr_ops = { "mipspmacfg14", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + {
> + .csrno = CSR_MIPSPMACFG15,
> + .csr_ops = { "mipspmacfg15", any, read_mipspmacfg, write_mipspmacfg }
> + },
> + { },
> +};
On 18. 6. 25. 19:59, Daniel Henrique Barboza wrote:
> [You don't often get email from dbarboza@ventanamicro.com. Learn why
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>
> CAUTION: This email originated from outside of the organization. Do
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>
> On 6/18/25 9:27 AM, Djordje Todorovic wrote:
>> Define MIPS CSRs used for P8700 CPU.
>>
>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> ---
>> target/riscv/cpu.c | 3 +
>> target/riscv/cpu.h | 12 +++
>> target/riscv/meson.build | 1 +
>> target/riscv/mips_csr.c | 219 +++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 235 insertions(+)
>> create mode 100644 target/riscv/mips_csr.c
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index be362e1644..1e85a16971 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -3179,6 +3179,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>> .cfg.ext_zba = true,
>> .cfg.ext_zbb = true,
>> .cfg.marchid = 0x8000000000000201,
>> +#ifndef CONFIG_USER_ONLY
>> + .custom_csrs = mips_csr_list,
>> +#endif
>> ),
>>
>> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index fba0b0506b..bf1a931e60 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -199,6 +199,13 @@ typedef struct PMUFixedCtrState {
>> uint64_t counter_virt_prev[2];
>> } PMUFixedCtrState;
>>
>> +struct MIPSCSR {
>> + uint64_t tvec;
>> + uint64_t config[12];
>> + uint64_t pmacfg[15];
>> +};
>> +typedef struct MIPSCSR MIPSCSR;
>> +
>> struct CPUArchState {
>> target_ulong gpr[32];
>> target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
>> @@ -497,6 +504,8 @@ struct CPUArchState {
>> target_ulong rnmip;
>> uint64_t rnmi_irqvec;
>> uint64_t rnmi_excpvec;
>> +
>> + MIPSCSR mips_csrs;
>
> I suggest a static MIPSCSR struct inside mips_csr.c so you can
> read/write the CSRs
> locally instead of adding MIPS-only attibutes in the common CPU state.
>
It makes sense, will do it in v4. Thanks a lot!
>
> Thanks,
>
> Daniel
>
>> };
>>
>> /*
>> @@ -972,5 +981,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool
>> is_32_bit);
>> /* In th_csr.c */
>> extern const RISCVCSR th_csr_list[];
>>
>> +/* Implemented in mips_csr.c */
>> +extern const RISCVCSR mips_csr_list[];
>> +
>> const char *priv_spec_to_str(int priv_version);
>> #endif /* RISCV_CPU_H */
>> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
>> index a4bd61e52a..fbb6c8fb45 100644
>> --- a/target/riscv/meson.build
>> +++ b/target/riscv/meson.build
>> @@ -32,6 +32,7 @@ riscv_system_ss.add(files(
>> 'debug.c',
>> 'monitor.c',
>> 'machine.c',
>> + 'mips_csr.c',
>> 'pmu.c',
>> 'th_csr.c',
>> 'time_helper.c',
>> diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c
>> new file mode 100644
>> index 0000000000..aab7f832a0
>> --- /dev/null
>> +++ b/target/riscv/mips_csr.c
>> @@ -0,0 +1,219 @@
>> +/*
>> + * MIPS-specific CSRs.
>> + *
>> + * Copyright (c) 2025 MIPS
>> + *
>> + * This program is free software; you can redistribute it and/or
>> modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but
>> WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of
>> MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
>> License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "cpu.h"
>> +#include "cpu_vendorid.h"
>> +
>> +/* MIPS CSR */
>> +#define CSR_MIPSTVEC 0x7c0
>> +#define CSR_MIPSCONFIG0 0x7d0
>> +#define CSR_MIPSCONFIG1 0x7d1
>> +#define CSR_MIPSCONFIG2 0x7d2
>> +#define CSR_MIPSCONFIG3 0x7d3
>> +#define CSR_MIPSCONFIG4 0x7d4
>> +#define CSR_MIPSCONFIG5 0x7d5
>> +#define CSR_MIPSCONFIG6 0x7d6
>> +#define CSR_MIPSCONFIG7 0x7d7
>> +#define CSR_MIPSCONFIG8 0x7d8
>> +#define CSR_MIPSCONFIG9 0x7d9
>> +#define CSR_MIPSCONFIG10 0x7da
>> +#define CSR_MIPSCONFIG11 0x7db
>> +#define CSR_MIPSPMACFG0 0x7e0
>> +#define CSR_MIPSPMACFG1 0x7e1
>> +#define CSR_MIPSPMACFG2 0x7e2
>> +#define CSR_MIPSPMACFG3 0x7e3
>> +#define CSR_MIPSPMACFG4 0x7e4
>> +#define CSR_MIPSPMACFG5 0x7e5
>> +#define CSR_MIPSPMACFG6 0x7e6
>> +#define CSR_MIPSPMACFG7 0x7e7
>> +#define CSR_MIPSPMACFG8 0x7e8
>> +#define CSR_MIPSPMACFG9 0x7e9
>> +#define CSR_MIPSPMACFG10 0x7ea
>> +#define CSR_MIPSPMACFG11 0x7eb
>> +#define CSR_MIPSPMACFG12 0x7ec
>> +#define CSR_MIPSPMACFG13 0x7ed
>> +#define CSR_MIPSPMACFG14 0x7ee
>> +#define CSR_MIPSPMACFG15 0x7ef
>> +
>> +static RISCVException any(CPURISCVState *env, int csrno)
>> +{
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException read_mipstvec(CPURISCVState *env, int csrno,
>> + target_ulong *val)
>> +{
>> + *val = env->mips_csrs.tvec;
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException write_mipstvec(CPURISCVState *env, int csrno,
>> + target_ulong val, uintptr_t ra)
>> +{
>> + env->mips_csrs.tvec = val;
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException read_mipsconfig(CPURISCVState *env, int csrno,
>> + target_ulong *val)
>> +{
>> + *val = env->mips_csrs.config[csrno - CSR_MIPSCONFIG0];
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException write_mipsconfig(CPURISCVState *env, int csrno,
>> + target_ulong val, uintptr_t ra)
>> +{
>> + env->mips_csrs.config[csrno - CSR_MIPSCONFIG0] = val;
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno,
>> + target_ulong *val)
>> +{
>> + *val = env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0];
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno,
>> + target_ulong val, uintptr_t ra)
>> +{
>> + env->mips_csrs.pmacfg[csrno - CSR_MIPSPMACFG0] = val;
>> + return RISCV_EXCP_NONE;
>> +}
>> +
>> +const RISCVCSR mips_csr_list[] = {
>> + {
>> + .csrno = CSR_MIPSTVEC,
>> + .csr_ops = { "mipstvec", any, read_mipstvec, write_mipstvec }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG0,
>> + .csr_ops = { "mipsconfig0", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG1,
>> + .csr_ops = { "mipsconfig1", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG2,
>> + .csr_ops = { "mipsconfig2", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG3,
>> + .csr_ops = { "mipsconfig3", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG4,
>> + .csr_ops = { "mipsconfig4", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG5,
>> + .csr_ops = { "mipsconfig5", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG6,
>> + .csr_ops = { "mipsconfig6", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG7,
>> + .csr_ops = { "mipsconfig7", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG8,
>> + .csr_ops = { "mipsconfig8", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG9,
>> + .csr_ops = { "mipsconfig9", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG10,
>> + .csr_ops = { "mipsconfig10", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSCONFIG11,
>> + .csr_ops = { "mipsconfig11", any, read_mipsconfig,
>> write_mipsconfig }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG0,
>> + .csr_ops = { "mipspmacfg0", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG1,
>> + .csr_ops = { "mipspmacfg1", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG2,
>> + .csr_ops = { "mipspmacfg2", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG3,
>> + .csr_ops = { "mipspmacfg3", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG4,
>> + .csr_ops = { "mipspmacfg4", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG5,
>> + .csr_ops = { "mipspmacfg5", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG6,
>> + .csr_ops = { "mipspmacfg6", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG7,
>> + .csr_ops = { "mipspmacfg7", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG8,
>> + .csr_ops = { "mipspmacfg8", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG9,
>> + .csr_ops = { "mipspmacfg9", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG10,
>> + .csr_ops = { "mipspmacfg10", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG11,
>> + .csr_ops = { "mipspmacfg11", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG12,
>> + .csr_ops = { "mipspmacfg12", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG13,
>> + .csr_ops = { "mipspmacfg13", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG14,
>> + .csr_ops = { "mipspmacfg14", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + {
>> + .csrno = CSR_MIPSPMACFG15,
>> + .csr_ops = { "mipspmacfg15", any, read_mipspmacfg,
>> write_mipspmacfg }
>> + },
>> + { },
>> +};
>
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