[RFC PATCH v3 0/2] cxl: Support creation of a new CXL Host Bridge

wangyuquan posted 2 patches 5 months ago
Failed in applying to current master (apply log)
Maintainers: Jonathan Cameron <jonathan.cameron@huawei.com>, Fan Ni <fan.ni@samsung.com>, "Michael S. Tsirkin" <mst@redhat.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Paolo Bonzini <pbonzini@redhat.com>
There is a newer version of this series
hw/cxl/cxl-host-stubs.c               |   3 +
hw/cxl/cxl-host.c                     |  64 ++++++++---
hw/pci-bridge/pci_expander_bridge.c   |   8 +-
hw/pci-host/Kconfig                   |   4 +
hw/pci-host/cxl.c                     | 152 ++++++++++++++++++++++++++
hw/pci-host/meson.build               |   1 +
include/hw/cxl/cxl.h                  |   7 +-
include/hw/cxl/cxl_host.h             |   3 +
include/hw/pci-host/cxl_host_bridge.h |  23 ++++
9 files changed, 244 insertions(+), 21 deletions(-)
create mode 100644 hw/pci-host/cxl.c
create mode 100644 include/hw/pci-host/cxl_host_bridge.h
[RFC PATCH v3 0/2] cxl: Support creation of a new CXL Host Bridge
Posted by wangyuquan 5 months ago
v2 -> v3:
- Update the commit message
- Fix some alignment and space problems
- Add a SPDX header for the new file
- Remove unnecessary comments
- Add CXL_HOST_BRIDGE config
v1 -> v2:
- Move the code of new bridge to hw/pci-host/cxl.c
- Fix and simplify some logic on handling the different bridge types

Background
==========
Currently the base CXL support for arm platforms is only on Jonathan's
patches[1]. Some platform like SBSA-REF can be more like a real machine,
thus the support of CXL could be meaningful. However, the pxb-cxl-host
realization on this platform seems not satisfying their requirements[2].

New CXL HOST design
===================
Defines a new CXL host bridge type (TYPE_CXL_HOST). This is an
independent CXL host bridge which combined GPEX features (ECAM, MMIO
windows and irq) and CXL Host Bridge Component Registers (CHBCR).

The root bus path of CXL_HOST is "0001:00", that would not affect the
original pcie host topology. In the previous, the pxb-cxl-host with
any CXL root ports and CXL endpoint devices would occupy the BDF
number of the original pcie domain. This new type provide a solution
to resolve the problem.

Remaining problems
==================
I tried to use 'object_resolve_path' but it could not work in
'cxl_fmws_link_targets', so I used 'TYPE_DEVICE' to match that.

Link:
[1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@huawei.com/
[2]: https://lists.nongnu.org/archive/html/qemu-arm/2024-11/msg00522.html

Yuquan Wang (2):
  pci-host/cxl: Support creation of a new CXL Host Bridge
  hw/pxb-cxl: Rename the pxb cxl host bridge

 hw/cxl/cxl-host-stubs.c               |   3 +
 hw/cxl/cxl-host.c                     |  64 ++++++++---
 hw/pci-bridge/pci_expander_bridge.c   |   8 +-
 hw/pci-host/Kconfig                   |   4 +
 hw/pci-host/cxl.c                     | 152 ++++++++++++++++++++++++++
 hw/pci-host/meson.build               |   1 +
 include/hw/cxl/cxl.h                  |   7 +-
 include/hw/cxl/cxl_host.h             |   3 +
 include/hw/pci-host/cxl_host_bridge.h |  23 ++++
 9 files changed, 244 insertions(+), 21 deletions(-)
 create mode 100644 hw/pci-host/cxl.c
 create mode 100644 include/hw/pci-host/cxl_host_bridge.h

-- 
2.34.1
Re: [RFC PATCH v3 0/2] cxl: Support creation of a new CXL Host Bridge
Posted by Dave Jiang 3 months, 3 weeks ago

On 6/16/25 9:06 PM, wangyuquan wrote:
> v2 -> v3:
> - Update the commit message
> - Fix some alignment and space problems
> - Add a SPDX header for the new file
> - Remove unnecessary comments
> - Add CXL_HOST_BRIDGE config
> v1 -> v2:
> - Move the code of new bridge to hw/pci-host/cxl.c
> - Fix and simplify some logic on handling the different bridge types

Hi Yuquan, can you please add qemu to your patch subject prefix in the future? i.e. [QEMU PATCH v4 0/2]. It would help the maintainers on linux-cxl to know they are not kernel patches. Thank you!

> 
> Background
> ==========
> Currently the base CXL support for arm platforms is only on Jonathan's
> patches[1]. Some platform like SBSA-REF can be more like a real machine,
> thus the support of CXL could be meaningful. However, the pxb-cxl-host
> realization on this platform seems not satisfying their requirements[2].
> 
> New CXL HOST design
> ===================
> Defines a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
> 
> The root bus path of CXL_HOST is "0001:00", that would not affect the
> original pcie host topology. In the previous, the pxb-cxl-host with
> any CXL root ports and CXL endpoint devices would occupy the BDF
> number of the original pcie domain. This new type provide a solution
> to resolve the problem.
> 
> Remaining problems
> ==================
> I tried to use 'object_resolve_path' but it could not work in
> 'cxl_fmws_link_targets', so I used 'TYPE_DEVICE' to match that.
> 
> Link:
> [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@huawei.com/
> [2]: https://lists.nongnu.org/archive/html/qemu-arm/2024-11/msg00522.html
> 
> Yuquan Wang (2):
>   pci-host/cxl: Support creation of a new CXL Host Bridge
>   hw/pxb-cxl: Rename the pxb cxl host bridge
> 
>  hw/cxl/cxl-host-stubs.c               |   3 +
>  hw/cxl/cxl-host.c                     |  64 ++++++++---
>  hw/pci-bridge/pci_expander_bridge.c   |   8 +-
>  hw/pci-host/Kconfig                   |   4 +
>  hw/pci-host/cxl.c                     | 152 ++++++++++++++++++++++++++
>  hw/pci-host/meson.build               |   1 +
>  include/hw/cxl/cxl.h                  |   7 +-
>  include/hw/cxl/cxl_host.h             |   3 +
>  include/hw/pci-host/cxl_host_bridge.h |  23 ++++
>  9 files changed, 244 insertions(+), 21 deletions(-)
>  create mode 100644 hw/pci-host/cxl.c
>  create mode 100644 include/hw/pci-host/cxl_host_bridge.h
>