[PATCH 06/19] hw/i3c/dw-i3c: Add more reset values

Joe Komlodi posted 19 patches 8 months ago
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, "Cédric Le Goater" <clg@kaod.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Jamin Lin <jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Daniel P. Berrangé" <berrange@redhat.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>
There is a newer version of this series
[PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
Posted by Joe Komlodi 8 months ago
Adds reset values for the new registers added.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
---
 hw/i3c/dw-i3c.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index b252903ea4..845fbd5efd 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
@@ -285,14 +285,32 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
     FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
 
 static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
-    [R_HW_CAPABILITY]               = 0x000e00bf,
+    /* Target mode is not supported, don't advertise it for now. */
+    [R_HW_CAPABILITY]               = 0x000e00b9,
     [R_QUEUE_THLD_CTRL]             = 0x01000101,
+    [R_DATA_BUFFER_THLD_CTRL]       = 0x01010100,
+    [R_SLV_EVENT_CTRL]              = 0x0000000b,
+    [R_QUEUE_STATUS_LEVEL]          = 0x00000002,
+    [R_DATA_BUFFER_STATUS_LEVEL]    = 0x00000010,
+    [R_PRESENT_STATE]               = 0x00000003,
     [R_I3C_VER_ID]                  = 0x3130302a,
     [R_I3C_VER_TYPE]                = 0x6c633033,
     [R_DEVICE_ADDR_TABLE_POINTER]   = 0x00080280,
     [R_DEV_CHAR_TABLE_POINTER]      = 0x00020200,
+    [R_SLV_CHAR_CTRL]               = 0x00010000,
     [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
     [R_SLV_MAX_LEN]                 = 0x00ff00ff,
+    [R_SLV_TSX_SYMBL_TIMING]        = 0x0000003f,
+    [R_SCL_I3C_OD_TIMING]           = 0x000a0010,
+    [R_SCL_I3C_PP_TIMING]           = 0x000a000a,
+    [R_SCL_I2C_FM_TIMING]           = 0x00100010,
+    [R_SCL_I2C_FMP_TIMING]          = 0x00100010,
+    [R_SCL_EXT_LCNT_TIMING]         = 0x20202020,
+    [R_SCL_EXT_TERMN_LCNT_TIMING]   = 0x00300000,
+    [R_BUS_FREE_TIMING]             = 0x00200020,
+    [R_BUS_IDLE_TIMING]             = 0x00000020,
+    [R_EXTENDED_CAPABILITY]         = 0x00000239,
+    [R_SLAVE_CONFIG]                = 0x00000023,
 };
 
 static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
-- 
2.50.0.rc1.591.g9c95f17f64-goog
RE: [PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
Posted by Jamin Lin 1 month ago
> Subject: [PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
> 
> Adds reset values for the new registers added.
> 
> Signed-off-by: Joe Komlodi <komlodi@google.com>
> 
> Reviewed-by: Patrick Venture <venture@google.com>
> ---
>  hw/i3c/dw-i3c.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index b252903ea4..845fbd5efd
> 100644
> --- a/hw/i3c/dw-i3c.c
> +++ b/hw/i3c/dw-i3c.c
> @@ -285,14 +285,32 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
>      FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
> 
>  static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
> -    [R_HW_CAPABILITY]               = 0x000e00bf,
> +    /* Target mode is not supported, don't advertise it for now. */
> +    [R_HW_CAPABILITY]               = 0x000e00b9,
>      [R_QUEUE_THLD_CTRL]             = 0x01000101,
> +    [R_DATA_BUFFER_THLD_CTRL]       = 0x01010100,
> +    [R_SLV_EVENT_CTRL]              = 0x0000000b,
> +    [R_QUEUE_STATUS_LEVEL]          = 0x00000002,
> +    [R_DATA_BUFFER_STATUS_LEVEL]    = 0x00000010,
> +    [R_PRESENT_STATE]               = 0x00000003,
>      [R_I3C_VER_ID]                  = 0x3130302a,
>      [R_I3C_VER_TYPE]                = 0x6c633033,
>      [R_DEVICE_ADDR_TABLE_POINTER]   = 0x00080280,
>      [R_DEV_CHAR_TABLE_POINTER]      = 0x00020200,
> +    [R_SLV_CHAR_CTRL]               = 0x00010000,
>      [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
>      [R_SLV_MAX_LEN]                 = 0x00ff00ff,
> +    [R_SLV_TSX_SYMBL_TIMING]        = 0x0000003f,
> +    [R_SCL_I3C_OD_TIMING]           = 0x000a0010,
> +    [R_SCL_I3C_PP_TIMING]           = 0x000a000a,
> +    [R_SCL_I2C_FM_TIMING]           = 0x00100010,
> +    [R_SCL_I2C_FMP_TIMING]          = 0x00100010,
> +    [R_SCL_EXT_LCNT_TIMING]         = 0x20202020,
> +    [R_SCL_EXT_TERMN_LCNT_TIMING]   = 0x00300000,
> +    [R_BUS_FREE_TIMING]             = 0x00200020,
> +    [R_BUS_IDLE_TIMING]             = 0x00000020,
> +    [R_EXTENDED_CAPABILITY]         = 0x00000239,
> +    [R_SLAVE_CONFIG]                = 0x00000023,
>  };
> 
>  static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
> --
> 2.50.0.rc1.591.g9c95f17f64-goog

Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>

Thanks,
Jamin

RE: [PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
Posted by Jamin Lin 1 month ago
Hi Joe,

> Subject: RE: [PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
> 
> > Subject: [PATCH 06/19] hw/i3c/dw-i3c: Add more reset values
> >
> > Adds reset values for the new registers added.
> >
> > Signed-off-by: Joe Komlodi <komlodi@google.com>
> >
> > Reviewed-by: Patrick Venture <venture@google.com>
> > ---
> >  hw/i3c/dw-i3c.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index b252903ea4..845fbd5efd
> > 100644
> > --- a/hw/i3c/dw-i3c.c
> > +++ b/hw/i3c/dw-i3c.c
> > @@ -285,14 +285,32 @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)
> >      FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)
> >
> >  static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {
> > -    [R_HW_CAPABILITY]               = 0x000e00bf,
> > +    /* Target mode is not supported, don't advertise it for now. */
> > +    [R_HW_CAPABILITY]               = 0x000e00b9,
> >      [R_QUEUE_THLD_CTRL]             = 0x01000101,
> > +    [R_DATA_BUFFER_THLD_CTRL]       = 0x01010100,
> > +    [R_SLV_EVENT_CTRL]              = 0x0000000b,
> > +    [R_QUEUE_STATUS_LEVEL]          = 0x00000002,
> > +    [R_DATA_BUFFER_STATUS_LEVEL]    = 0x00000010,
> > +    [R_PRESENT_STATE]               = 0x00000003,
> >      [R_I3C_VER_ID]                  = 0x3130302a,
> >      [R_I3C_VER_TYPE]                = 0x6c633033,
> >      [R_DEVICE_ADDR_TABLE_POINTER]   = 0x00080280,
> >      [R_DEV_CHAR_TABLE_POINTER]      = 0x00020200,
> > +    [R_SLV_CHAR_CTRL]               = 0x00010000,
> >      [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
> >      [R_SLV_MAX_LEN]                 = 0x00ff00ff,
> > +    [R_SLV_TSX_SYMBL_TIMING]        = 0x0000003f,


I don’t see this register defined in the datasheet.
Which document are you referencing for this member?

> > +    [R_SCL_I3C_OD_TIMING]           = 0x000a0010,
> > +    [R_SCL_I3C_PP_TIMING]           = 0x000a000a,
> > +    [R_SCL_I2C_FM_TIMING]           = 0x00100010,
> > +    [R_SCL_I2C_FMP_TIMING]          = 0x00100010,
> > +    [R_SCL_EXT_LCNT_TIMING]         = 0x20202020,
> > +    [R_SCL_EXT_TERMN_LCNT_TIMING]   = 0x00300000,
> > +    [R_BUS_FREE_TIMING]             = 0x00200020,
> > +    [R_BUS_IDLE_TIMING]             = 0x00000020,
> > +    [R_EXTENDED_CAPABILITY]         = 0x00000239,


I don’t see this register defined in the datasheet.
Which document are you referencing for this member?

> > +    [R_SLAVE_CONFIG]                = 0x00000023,


I don’t see this register defined in the datasheet.
Which document are you referencing for this member?

> >  };
> >
> >  static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
> > --
> > 2.50.0.rc1.591.g9c95f17f64-goog
> 
> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
> 
> Thanks,
> Jamin