[v1] i3c: aspeed: Add I3C support

[PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Joe Komlodi 7 months, 4 weeks ago

Hi all,

This series adds I3C bus support to QEMU and adds more functionality to the
Aspeed I3C controller.

This implementation is a basic implementation that introduces IBIs
(including hot-join), CCCs, and SDR data transfer. As-is, it doesn't support
multi-controller buses or HDR transfers.

First we add the I3C bus and controller model. With that added we extend
the functionality of the Aspeed I3C controller so it can do transfers
and handle IBIs.

Next, we add a mock I3C target. It's intended to be a very simple target
just to verify that I3C is working on the guest. Internally, we've used it
on Linux to verify that i3C devices can be probed and can send/receive data
and IBIs.
This target is sort of like an EEPROM, and it can also send IBIs upon
reception of a user-defined magic number.

Lastly we add  hotplugging support. The hotplugging doesn't do anything too
complicated, it just adds the device attempting to hotplug to the bus. It
is the device's responsibility to hot-join and go through the DAA process
to participate on the bus.

Thanks,
Joe

Joe Komlodi (19):
  hw/misc/aspeed_i3c: Move to i3c directory
  hw/i3c: Add bus support
  hw/i3c: Split DesignWare I3C out of Aspeed I3C
  hw/i3c/dw-i3c: Add more register fields
  hw/i3c/aspeed_i3c: Add more register fields
  hw/i3c/dw-i3c: Add more reset values
  hw/i3c/aspeed_i3c: Add register RO field masks
  hw/i3c/dw-i3c: Add register RO field masks
  hw/i3c/dw-i3c: Treat more registers as read-as-zero
  hw/i3c/dw-i3c: Use 32 bits on MMIO writes
  hw/i3c/dw-i3c: Add IRQ MMIO behavior
  hw/i3c/dw-i3c: Add data TX and RX
  hw/i3c/dw-i3c: Add IBI handling
  hw/i3c/dw-i3c: Add ctrl MMIO handling
  hw/i3c/dw-i3c: Add controller resets
  hw/i3c/aspeed: Add I3C bus get function
  hw/i3c: Add Mock target
  hw/arm/aspeed: Build with I3C_DEVICES
  hw/i3c: Add hotplug support

 hw/Kconfig                            |    1 +
 hw/arm/Kconfig                        |    3 +
 hw/i3c/Kconfig                        |   15 +
 hw/i3c/aspeed_i3c.c                   |  261 ++++
 hw/i3c/core.c                         |  669 +++++++++
 hw/i3c/dw-i3c.c                       | 1881 +++++++++++++++++++++++++
 hw/i3c/meson.build                    |    6 +
 hw/i3c/mock-i3c-target.c              |  311 ++++
 hw/i3c/trace-events                   |   47 +
 hw/i3c/trace.h                        |    2 +
 hw/meson.build                        |    1 +
 hw/misc/aspeed_i3c.c                  |  383 -----
 hw/misc/meson.build                   |    1 -
 hw/misc/trace-events                  |    6 -
 include/hw/arm/aspeed_soc.h           |    2 +-
 include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
 include/hw/i3c/dw-i3c.h               |  201 +++
 include/hw/i3c/i3c.h                  |  277 ++++
 include/hw/i3c/mock-i3c-target.h      |   52 +
 meson.build                           |    1 +
 20 files changed, 3735 insertions(+), 407 deletions(-)
 create mode 100644 hw/i3c/Kconfig
 create mode 100644 hw/i3c/aspeed_i3c.c
 create mode 100644 hw/i3c/core.c
 create mode 100644 hw/i3c/dw-i3c.c
 create mode 100644 hw/i3c/meson.build
 create mode 100644 hw/i3c/mock-i3c-target.c
 create mode 100644 hw/i3c/trace-events
 create mode 100644 hw/i3c/trace.h
 delete mode 100644 hw/misc/aspeed_i3c.c
 rename include/hw/{misc => i3c}/aspeed_i3c.h (63%)
 create mode 100644 include/hw/i3c/dw-i3c.h
 create mode 100644 include/hw/i3c/i3c.h
 create mode 100644 include/hw/i3c/mock-i3c-target.h

-- 
2.50.0.rc1.591.g9c95f17f64-goog

Re: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Cédric Le Goater 7 months, 3 weeks ago

Hi

+ Jeremy

On 6/13/25 02:03, Joe Komlodi wrote:
> Hi all,
> 
> This series adds I3C bus support to QEMU and adds more functionality to the
> Aspeed I3C controller.
> 
> This implementation is a basic implementation that introduces IBIs
> (including hot-join), CCCs, and SDR data transfer. As-is, it doesn't support
> multi-controller buses or HDR transfers.
> 
> First we add the I3C bus and controller model. With that added we extend
> the functionality of the Aspeed I3C controller so it can do transfers
> and handle IBIs.
> 
> Next, we add a mock I3C target. It's intended to be a very simple target
> just to verify that I3C is working on the guest. Internally, we've used it
> on Linux to verify that i3C devices can be probed and can send/receive data
> and IBIs.
> This target is sort of like an EEPROM, and it can also send IBIs upon
> reception of a user-defined magic number.> 
> Lastly we add  hotplugging support. The hotplugging doesn't do anything too
> complicated, it just adds the device attempting to hotplug to the bus. It
> is the device's responsibility to hot-join and go through the DAA process
> to participate on the bus.
> 
> Thanks,
> Joe
> 
> Joe Komlodi (19):
>    hw/misc/aspeed_i3c: Move to i3c directory
>    hw/i3c: Add bus support
>    hw/i3c: Split DesignWare I3C out of Aspeed I3C
>    hw/i3c/dw-i3c: Add more register fields
>    hw/i3c/aspeed_i3c: Add more register fields
>    hw/i3c/dw-i3c: Add more reset values
>    hw/i3c/aspeed_i3c: Add register RO field masks
>    hw/i3c/dw-i3c: Add register RO field masks
>    hw/i3c/dw-i3c: Treat more registers as read-as-zero
>    hw/i3c/dw-i3c: Use 32 bits on MMIO writes
>    hw/i3c/dw-i3c: Add IRQ MMIO behavior
>    hw/i3c/dw-i3c: Add data TX and RX
>    hw/i3c/dw-i3c: Add IBI handling
>    hw/i3c/dw-i3c: Add ctrl MMIO handling
>    hw/i3c/dw-i3c: Add controller resets
>    hw/i3c/aspeed: Add I3C bus get function
>    hw/i3c: Add Mock target
>    hw/arm/aspeed: Build with I3C_DEVICES
>    hw/i3c: Add hotplug support
> 
>   hw/Kconfig                            |    1 +
>   hw/arm/Kconfig                        |    3 +
>   hw/i3c/Kconfig                        |   15 +
>   hw/i3c/aspeed_i3c.c                   |  261 ++++
>   hw/i3c/core.c                         |  669 +++++++++
>   hw/i3c/dw-i3c.c                       | 1881 +++++++++++++++++++++++++
>   hw/i3c/meson.build                    |    6 +
>   hw/i3c/mock-i3c-target.c              |  311 ++++
>   hw/i3c/trace-events                   |   47 +
>   hw/i3c/trace.h                        |    2 +
>   hw/meson.build                        |    1 +
>   hw/misc/aspeed_i3c.c                  |  383 -----
>   hw/misc/meson.build                   |    1 -
>   hw/misc/trace-events                  |    6 -
>   include/hw/arm/aspeed_soc.h           |    2 +-
>   include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
>   include/hw/i3c/dw-i3c.h               |  201 +++
>   include/hw/i3c/i3c.h                  |  277 ++++
>   include/hw/i3c/mock-i3c-target.h      |   52 +
>   meson.build                           |    1 +
>   20 files changed, 3735 insertions(+), 407 deletions(-)
>   create mode 100644 hw/i3c/Kconfig
>   create mode 100644 hw/i3c/aspeed_i3c.c
>   create mode 100644 hw/i3c/core.c
>   create mode 100644 hw/i3c/dw-i3c.c
>   create mode 100644 hw/i3c/meson.build
>   create mode 100644 hw/i3c/mock-i3c-target.c
>   create mode 100644 hw/i3c/trace-events
>   create mode 100644 hw/i3c/trace.h
>   delete mode 100644 hw/misc/aspeed_i3c.c
>   rename include/hw/{misc => i3c}/aspeed_i3c.h (63%)
>   create mode 100644 include/hw/i3c/dw-i3c.h
>   create mode 100644 include/hw/i3c/i3c.h
>   create mode 100644 include/hw/i3c/mock-i3c-target.h
> 

This lacks a MAINTAINER.

Could you please provide functional tests ? some with a standard I2C
device attached to an I3C legacy bus too.

Are there any other stakeholders interested in the I3C to get feedback ?

Have there been any changes since:

   https://lore.kernel.org/qemu-devel/20230331010131.1412571-1-komlodi@google.com/

Thanks,

C.

Re: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Joe Komlodi 7 months, 3 weeks ago

Hi,

On Sun, Jun 15, 2025 at 11:49 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> Hi
>
> + Jeremy
>
> On 6/13/25 02:03, Joe Komlodi wrote:
> > Hi all,
> >
> > This series adds I3C bus support to QEMU and adds more functionality to the
> > Aspeed I3C controller.
> >
> > This implementation is a basic implementation that introduces IBIs
> > (including hot-join), CCCs, and SDR data transfer. As-is, it doesn't support
> > multi-controller buses or HDR transfers.
> >
> > First we add the I3C bus and controller model. With that added we extend
> > the functionality of the Aspeed I3C controller so it can do transfers
> > and handle IBIs.
> >
> > Next, we add a mock I3C target. It's intended to be a very simple target
> > just to verify that I3C is working on the guest. Internally, we've used it
> > on Linux to verify that i3C devices can be probed and can send/receive data
> > and IBIs.
> > This target is sort of like an EEPROM, and it can also send IBIs upon
> > reception of a user-defined magic number.>
> > Lastly we add  hotplugging support. The hotplugging doesn't do anything too
> > complicated, it just adds the device attempting to hotplug to the bus. It
> > is the device's responsibility to hot-join and go through the DAA process
> > to participate on the bus.
> >
> > Thanks,
> > Joe
> >
> > Joe Komlodi (19):
> >    hw/misc/aspeed_i3c: Move to i3c directory
> >    hw/i3c: Add bus support
> >    hw/i3c: Split DesignWare I3C out of Aspeed I3C
> >    hw/i3c/dw-i3c: Add more register fields
> >    hw/i3c/aspeed_i3c: Add more register fields
> >    hw/i3c/dw-i3c: Add more reset values
> >    hw/i3c/aspeed_i3c: Add register RO field masks
> >    hw/i3c/dw-i3c: Add register RO field masks
> >    hw/i3c/dw-i3c: Treat more registers as read-as-zero
> >    hw/i3c/dw-i3c: Use 32 bits on MMIO writes
> >    hw/i3c/dw-i3c: Add IRQ MMIO behavior
> >    hw/i3c/dw-i3c: Add data TX and RX
> >    hw/i3c/dw-i3c: Add IBI handling
> >    hw/i3c/dw-i3c: Add ctrl MMIO handling
> >    hw/i3c/dw-i3c: Add controller resets
> >    hw/i3c/aspeed: Add I3C bus get function
> >    hw/i3c: Add Mock target
> >    hw/arm/aspeed: Build with I3C_DEVICES
> >    hw/i3c: Add hotplug support
> >
> >   hw/Kconfig                            |    1 +
> >   hw/arm/Kconfig                        |    3 +
> >   hw/i3c/Kconfig                        |   15 +
> >   hw/i3c/aspeed_i3c.c                   |  261 ++++
> >   hw/i3c/core.c                         |  669 +++++++++
> >   hw/i3c/dw-i3c.c                       | 1881 +++++++++++++++++++++++++
> >   hw/i3c/meson.build                    |    6 +
> >   hw/i3c/mock-i3c-target.c              |  311 ++++
> >   hw/i3c/trace-events                   |   47 +
> >   hw/i3c/trace.h                        |    2 +
> >   hw/meson.build                        |    1 +
> >   hw/misc/aspeed_i3c.c                  |  383 -----
> >   hw/misc/meson.build                   |    1 -
> >   hw/misc/trace-events                  |    6 -
> >   include/hw/arm/aspeed_soc.h           |    2 +-
> >   include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
> >   include/hw/i3c/dw-i3c.h               |  201 +++
> >   include/hw/i3c/i3c.h                  |  277 ++++
> >   include/hw/i3c/mock-i3c-target.h      |   52 +
> >   meson.build                           |    1 +
> >   20 files changed, 3735 insertions(+), 407 deletions(-)
> >   create mode 100644 hw/i3c/Kconfig
> >   create mode 100644 hw/i3c/aspeed_i3c.c
> >   create mode 100644 hw/i3c/core.c
> >   create mode 100644 hw/i3c/dw-i3c.c
> >   create mode 100644 hw/i3c/meson.build
> >   create mode 100644 hw/i3c/mock-i3c-target.c
> >   create mode 100644 hw/i3c/trace-events
> >   create mode 100644 hw/i3c/trace.h
> >   delete mode 100644 hw/misc/aspeed_i3c.c
> >   rename include/hw/{misc => i3c}/aspeed_i3c.h (63%)
> >   create mode 100644 include/hw/i3c/dw-i3c.h
> >   create mode 100644 include/hw/i3c/i3c.h
> >   create mode 100644 include/hw/i3c/mock-i3c-target.h
> >
>
> This lacks a MAINTAINER.

Ah, right. I can add that in v2. I can add myself to it, is there
anyone else who should be on it?
>
> Could you please provide functional tests ? some with a standard I2C
> device attached to an I3C legacy bus too.

I can work on that, probably v2 or v3 depending on how long it takes.
>
> Are there any other stakeholders interested in the I3C to get feedback ?
>
> Have there been any changes since:
>
>    https://lore.kernel.org/qemu-devel/20230331010131.1412571-1-komlodi@google.com/
>
Nothing too substantial. I decided not to upstream remote I3C since
it's unlikely it would be useful upstream.
I think there might be a couple bugfixes in the DwC controller as
well, but I don't remember off-hand what they were. If there were any,
they were all minor.

Thanks,
Joe

> Thanks,
>
> C.

Re: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Cédric Le Goater 7 months, 3 weeks ago

Hi,

>> This lacks a MAINTAINER.
> 
> Ah, right. I can add that in v2. I can add myself to it, is there
> anyone else who should be on it?

Would any of your colleagues be interested too ?

>> Could you please provide functional tests ? some with a standard I2C
>> device attached to an I3C legacy bus too.
> 
> I can work on that, probably v2 or v3 depending on how long it takes.

It can come later.

>> Are there any other stakeholders interested in the I3C to get feedback ?
>>
>> Have there been any changes since:
>>
>>     https://lore.kernel.org/qemu-devel/20230331010131.1412571-1-komlodi@google.com/
>>
> Nothing too substantial. I decided not to upstream remote I3C since
> it's unlikely it would be useful upstream.
>
> I think there might be a couple bugfixes in the DwC controller as
> well, but I don't remember off-hand what they were. If there were any,
> they were all minor.
The code looks code AFAICT but we need someone with a minimum I3C
knowledge to take a look. Could the Linux maintainers help review
this series ?

Thanks,

C.

Re: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Cédric Le Goater 1 month ago

Hello Joe,

On 6/13/25 02:03, Joe Komlodi wrote:
> Hi all,
> 
> This series adds I3C bus support to QEMU and adds more functionality to the
> Aspeed I3C controller.
> 
> This implementation is a basic implementation that introduces IBIs
> (including hot-join), CCCs, and SDR data transfer. As-is, it doesn't support
> multi-controller buses or HDR transfers.
> 
> First we add the I3C bus and controller model. With that added we extend
> the functionality of the Aspeed I3C controller so it can do transfers
> and handle IBIs.
> 
> Next, we add a mock I3C target. It's intended to be a very simple target
> just to verify that I3C is working on the guest. Internally, we've used it
> on Linux to verify that i3C devices can be probed and can send/receive data
> and IBIs.
> This target is sort of like an EEPROM, and it can also send IBIs upon
> reception of a user-defined magic number.
> 
> Lastly we add  hotplugging support. The hotplugging doesn't do anything too
> complicated, it just adds the device attempting to hotplug to the bus. It
> is the device's responsibility to hot-join and go through the DAA process
> to participate on the bus.
> 
> Thanks,
> Joe
> 
> Joe Komlodi (19):
>    hw/misc/aspeed_i3c: Move to i3c directory
>    hw/i3c: Add bus support
>    hw/i3c: Split DesignWare I3C out of Aspeed I3C
>    hw/i3c/dw-i3c: Add more register fields
>    hw/i3c/aspeed_i3c: Add more register fields
>    hw/i3c/dw-i3c: Add more reset values
>    hw/i3c/aspeed_i3c: Add register RO field masks
>    hw/i3c/dw-i3c: Add register RO field masks
>    hw/i3c/dw-i3c: Treat more registers as read-as-zero
>    hw/i3c/dw-i3c: Use 32 bits on MMIO writes
>    hw/i3c/dw-i3c: Add IRQ MMIO behavior
>    hw/i3c/dw-i3c: Add data TX and RX
>    hw/i3c/dw-i3c: Add IBI handling
>    hw/i3c/dw-i3c: Add ctrl MMIO handling
>    hw/i3c/dw-i3c: Add controller resets
>    hw/i3c/aspeed: Add I3C bus get function
>    hw/i3c: Add Mock target
>    hw/arm/aspeed: Build with I3C_DEVICES
>    hw/i3c: Add hotplug support
> 
>   hw/Kconfig                            |    1 +
>   hw/arm/Kconfig                        |    3 +
>   hw/i3c/Kconfig                        |   15 +
>   hw/i3c/aspeed_i3c.c                   |  261 ++++
>   hw/i3c/core.c                         |  669 +++++++++
>   hw/i3c/dw-i3c.c                       | 1881 +++++++++++++++++++++++++
>   hw/i3c/meson.build                    |    6 +
>   hw/i3c/mock-i3c-target.c              |  311 ++++
>   hw/i3c/trace-events                   |   47 +
>   hw/i3c/trace.h                        |    2 +
>   hw/meson.build                        |    1 +
>   hw/misc/aspeed_i3c.c                  |  383 -----
>   hw/misc/meson.build                   |    1 -
>   hw/misc/trace-events                  |    6 -
>   include/hw/arm/aspeed_soc.h           |    2 +-
>   include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
>   include/hw/i3c/dw-i3c.h               |  201 +++
>   include/hw/i3c/i3c.h                  |  277 ++++
>   include/hw/i3c/mock-i3c-target.h      |   52 +
>   meson.build                           |    1 +
>   20 files changed, 3735 insertions(+), 407 deletions(-)
>   create mode 100644 hw/i3c/Kconfig
>   create mode 100644 hw/i3c/aspeed_i3c.c
>   create mode 100644 hw/i3c/core.c
>   create mode 100644 hw/i3c/dw-i3c.c
>   create mode 100644 hw/i3c/meson.build
>   create mode 100644 hw/i3c/mock-i3c-target.c
>   create mode 100644 hw/i3c/trace-events
>   create mode 100644 hw/i3c/trace.h
>   delete mode 100644 hw/misc/aspeed_i3c.c
>   rename include/hw/{misc => i3c}/aspeed_i3c.h (63%)
>   create mode 100644 include/hw/i3c/dw-i3c.h
>   create mode 100644 include/hw/i3c/i3c.h
>   create mode 100644 include/hw/i3c/mock-i3c-target.h
> 

Could you please resend a v2 with the R-b tags from Jamin ?

Thanks,

C.

RE: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Jamin Lin 1 month ago

Hi Joe,

> Subject: [PATCH 00/19] i3c: aspeed: Add I3C support
> 
> Hi all,
> 
> This series adds I3C bus support to QEMU and adds more functionality to the
> Aspeed I3C controller.
> 
> This implementation is a basic implementation that introduces IBIs (including
> hot-join), CCCs, and SDR data transfer. As-is, it doesn't support multi-controller
> buses or HDR transfers.
> 
> First we add the I3C bus and controller model. With that added we extend the
> functionality of the Aspeed I3C controller so it can do transfers and handle IBIs.
> 
> Next, we add a mock I3C target. It's intended to be a very simple target just to
> verify that I3C is working on the guest. Internally, we've used it on Linux to
> verify that i3C devices can be probed and can send/receive data and IBIs.
> This target is sort of like an EEPROM, and it can also send IBIs upon reception
> of a user-defined magic number.
> 
> Lastly we add  hotplugging support. The hotplugging doesn't do anything too
> complicated, it just adds the device attempting to hotplug to the bus. It is the
> device's responsibility to hot-join and go through the DAA process to
> participate on the bus.
> 
> Thanks,
> Joe
> 
> Joe Komlodi (19):
>   hw/misc/aspeed_i3c: Move to i3c directory
>   hw/i3c: Add bus support
>   hw/i3c: Split DesignWare I3C out of Aspeed I3C
>   hw/i3c/dw-i3c: Add more register fields
>   hw/i3c/aspeed_i3c: Add more register fields
>   hw/i3c/dw-i3c: Add more reset values
>   hw/i3c/aspeed_i3c: Add register RO field masks
>   hw/i3c/dw-i3c: Add register RO field masks
>   hw/i3c/dw-i3c: Treat more registers as read-as-zero
>   hw/i3c/dw-i3c: Use 32 bits on MMIO writes
>   hw/i3c/dw-i3c: Add IRQ MMIO behavior
>   hw/i3c/dw-i3c: Add data TX and RX
>   hw/i3c/dw-i3c: Add IBI handling
>   hw/i3c/dw-i3c: Add ctrl MMIO handling
>   hw/i3c/dw-i3c: Add controller resets
>   hw/i3c/aspeed: Add I3C bus get function
>   hw/i3c: Add Mock target
>   hw/arm/aspeed: Build with I3C_DEVICES
>   hw/i3c: Add hotplug support
> 
>  hw/Kconfig                            |    1 +
>  hw/arm/Kconfig                        |    3 +
>  hw/i3c/Kconfig                        |   15 +
>  hw/i3c/aspeed_i3c.c                   |  261 ++++
>  hw/i3c/core.c                         |  669 +++++++++
>  hw/i3c/dw-i3c.c                       | 1881
> +++++++++++++++++++++++++
>  hw/i3c/meson.build                    |    6 +
>  hw/i3c/mock-i3c-target.c              |  311 ++++
>  hw/i3c/trace-events                   |   47 +
>  hw/i3c/trace.h                        |    2 +
>  hw/meson.build                        |    1 +
>  hw/misc/aspeed_i3c.c                  |  383 -----
>  hw/misc/meson.build                   |    1 -
>  hw/misc/trace-events                  |    6 -
>  include/hw/arm/aspeed_soc.h           |    2 +-
>  include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
>  include/hw/i3c/dw-i3c.h               |  201 +++
>  include/hw/i3c/i3c.h                  |  277 ++++
>  include/hw/i3c/mock-i3c-target.h      |   52 +
>  meson.build                           |    1 +
>  20 files changed, 3735 insertions(+), 407 deletions(-)  create mode 100644
> hw/i3c/Kconfig  create mode 100644 hw/i3c/aspeed_i3c.c  create mode
> 100644 hw/i3c/core.c  create mode 100644 hw/i3c/dw-i3c.c  create mode
> 100644 hw/i3c/meson.build  create mode 100644 hw/i3c/mock-i3c-target.c
> create mode 100644 hw/i3c/trace-events  create mode 100644
> hw/i3c/trace.h  delete mode 100644 hw/misc/aspeed_i3c.c  rename
> include/hw/{misc => i3c}/aspeed_i3c.h (63%)  create mode 100644
> include/hw/i3c/dw-i3c.h  create mode 100644 include/hw/i3c/i3c.h  create
> mode 100644 include/hw/i3c/mock-i3c-target.h
> 
> --
> 2.50.0.rc1.591.g9c95f17f64-goog


I tested this series on AST2600, and the results are as follows:

1. QEMU command line
  Add the following option to the QEMU command line
  -device mock-i3c-target,bus=dw.i3c.5,buf-size=256,ibi-magic-num=0x5a

1. Device enumeration
  After booting into Linux, the new device appears on I3C bus 5:

root@ast2600-default:/sys/bus/i3c/devices# ls
0-4cc31020000  0-4cc51180000  0-4cc51181000  1-4cc31020000  1-4cc51180000  1-4cc51181000  4-target       5-0            i3c-0          i3c-1          i3c-2          i3c-3          i3c-4          i3c-5

1. READ/WRITE MOCK EEPROM
I verified private write and read operations using the i3cdev interface

root@ast2600-default:/sys/bus/i3c/devices/5-0# dd if=/tmp/jamin of=/dev/i3c-5-0
0+1 records in
0+1 records out
200 bytes (200B) copied, 0.002032 seconds, 96.1KB/s

root@ast2600-default:/sys/bus/i3c/devices/5-0# hexdump /dev/i3c-5-0
0000000 04cb 2d84 0d80 45e6 6c9a 3d23 9384 b3ef
0000010 f534 3328 5e07 ac94 5cd6 3914 86ad e085
0000020 e047 81e3 af52 bb88 f20c c282 6148 5374
0000030 6b7d 58bf fb1c 2382 121f 1a60 bfb4 1ebd
0000040 8028 0a82 4740 8287 5737 988f 597e 9a67
0000050 a7f7 b0c8 db87 2631 8304 df89 6977 2a82
0000060 12d8 fb73 bcc7 ecd0 eba2 575f a050 02fb
0000070 af4b ffef da5b 5cb3 14a3 7047 17ac d238
0000080 eda6 ae3e ac72 6112 bbbf fbca 844d 035e
0000090 0970 f591 7536 8312 0552 d4fd 817b b323
00000a0 398b e633 df77 59ee fd4e 6922 e4a9 a160
00000b0 d206 96e1 a915 782b 1b53 a9bc 70c6 5670
00000c0 6dfe a3de ca1f bd0a
00000c8

root@ast2600-default:/sys/bus/i3c/devices/5-0# hexdump /tmp/jamin
0000000 04cb 2d84 0d80 45e6 6c9a 3d23 9384 b3ef
0000010 f534 3328 5e07 ac94 5cd6 3914 86ad e085
0000020 e047 81e3 af52 bb88 f20c c282 6148 5374
0000030 6b7d 58bf fb1c 2382 121f 1a60 bfb4 1ebd
0000040 8028 0a82 4740 8287 5737 988f 597e 9a67
0000050 a7f7 b0c8 db87 2631 8304 df89 6977 2a82
0000060 12d8 fb73 bcc7 ecd0 eba2 575f a050 02fb
0000070 af4b ffef da5b 5cb3 14a3 7047 17ac d238
0000080 eda6 ae3e ac72 6112 bbbf fbca 844d 035e
0000090 0970 f591 7536 8312 0552 d4fd 817b b323
00000a0 398b e633 df77 59ee fd4e 6922 e4a9 a160
00000b0 d206 96e1 a915 782b 1b53 a9bc 70c6 5670
00000c0 6dfe a3de ca1f bd0a
00000c8

root@ast2600-default:/sys/bus/i3c/devices/5-0# dd if=/dev/i3c-5-0 bs=1 count=200 2>/dev/null | cmp - /tmp/jamin && echo "PASS" || echo "FAIL"
PASS

The data read back from /dev/i3c-5-0 matches the original file exactly, and the comparison reports PASS.
This confirms that the mock I3C target works correctly as an EEPROM-like device and that the TX/RX data path through the DW I3C controller model functions as expected on AST2600.

Thanks,
Jamin

RE: [PATCH 00/19] i3c: aspeed: Add I3C support

Posted by Jamin Lin 1 month ago

> Subject: RE: [PATCH 00/19] i3c: aspeed: Add I3C support
> 
> Hi Joe,
> 
> > Subject: [PATCH 00/19] i3c: aspeed: Add I3C support
> >
> > Hi all,
> >
> > This series adds I3C bus support to QEMU and adds more functionality
> > to the Aspeed I3C controller.
> >
> > This implementation is a basic implementation that introduces IBIs
> > (including hot-join), CCCs, and SDR data transfer. As-is, it doesn't
> > support multi-controller buses or HDR transfers.
> >
> > First we add the I3C bus and controller model. With that added we
> > extend the functionality of the Aspeed I3C controller so it can do transfers
> and handle IBIs.
> >
> > Next, we add a mock I3C target. It's intended to be a very simple
> > target just to verify that I3C is working on the guest. Internally,
> > we've used it on Linux to verify that i3C devices can be probed and can
> send/receive data and IBIs.
> > This target is sort of like an EEPROM, and it can also send IBIs upon
> > reception of a user-defined magic number.
> >
> > Lastly we add  hotplugging support. The hotplugging doesn't do
> > anything too complicated, it just adds the device attempting to
> > hotplug to the bus. It is the device's responsibility to hot-join and
> > go through the DAA process to participate on the bus.
> >
> > Thanks,
> > Joe
> >
> > Joe Komlodi (19):
> >   hw/misc/aspeed_i3c: Move to i3c directory
> >   hw/i3c: Add bus support
> >   hw/i3c: Split DesignWare I3C out of Aspeed I3C
> >   hw/i3c/dw-i3c: Add more register fields
> >   hw/i3c/aspeed_i3c: Add more register fields
> >   hw/i3c/dw-i3c: Add more reset values
> >   hw/i3c/aspeed_i3c: Add register RO field masks
> >   hw/i3c/dw-i3c: Add register RO field masks
> >   hw/i3c/dw-i3c: Treat more registers as read-as-zero
> >   hw/i3c/dw-i3c: Use 32 bits on MMIO writes
> >   hw/i3c/dw-i3c: Add IRQ MMIO behavior
> >   hw/i3c/dw-i3c: Add data TX and RX
> >   hw/i3c/dw-i3c: Add IBI handling
> >   hw/i3c/dw-i3c: Add ctrl MMIO handling
> >   hw/i3c/dw-i3c: Add controller resets
> >   hw/i3c/aspeed: Add I3C bus get function
> >   hw/i3c: Add Mock target
> >   hw/arm/aspeed: Build with I3C_DEVICES
> >   hw/i3c: Add hotplug support
> >
> >  hw/Kconfig                            |    1 +
> >  hw/arm/Kconfig                        |    3 +
> >  hw/i3c/Kconfig                        |   15 +
> >  hw/i3c/aspeed_i3c.c                   |  261 ++++
> >  hw/i3c/core.c                         |  669 +++++++++
> >  hw/i3c/dw-i3c.c                       | 1881
> > +++++++++++++++++++++++++
> >  hw/i3c/meson.build                    |    6 +
> >  hw/i3c/mock-i3c-target.c              |  311 ++++
> >  hw/i3c/trace-events                   |   47 +
> >  hw/i3c/trace.h                        |    2 +
> >  hw/meson.build                        |    1 +
> >  hw/misc/aspeed_i3c.c                  |  383 -----
> >  hw/misc/meson.build                   |    1 -
> >  hw/misc/trace-events                  |    6 -
> >  include/hw/arm/aspeed_soc.h           |    2 +-
> >  include/hw/{misc => i3c}/aspeed_i3c.h |   22 +-
> >  include/hw/i3c/dw-i3c.h               |  201 +++
> >  include/hw/i3c/i3c.h                  |  277 ++++
> >  include/hw/i3c/mock-i3c-target.h      |   52 +
> >  meson.build                           |    1 +
> >  20 files changed, 3735 insertions(+), 407 deletions(-)  create mode
> > 100644 hw/i3c/Kconfig  create mode 100644 hw/i3c/aspeed_i3c.c  create
> > mode
> > 100644 hw/i3c/core.c  create mode 100644 hw/i3c/dw-i3c.c  create mode
> > 100644 hw/i3c/meson.build  create mode 100644 hw/i3c/mock-i3c-target.c
> > create mode 100644 hw/i3c/trace-events  create mode 100644
> > hw/i3c/trace.h  delete mode 100644 hw/misc/aspeed_i3c.c  rename
> > include/hw/{misc => i3c}/aspeed_i3c.h (63%)  create mode 100644
> > include/hw/i3c/dw-i3c.h  create mode 100644 include/hw/i3c/i3c.h
> > create mode 100644 include/hw/i3c/mock-i3c-target.h
> >
> > --
> > 2.50.0.rc1.591.g9c95f17f64-goog
> 
> 
> I tested this series on AST2600, and the results are as follows:
> 
> 1. QEMU command line
>   Add the following option to the QEMU command line
>   -device mock-i3c-target,bus=dw.i3c.5,buf-size=256,ibi-magic-num=0x5a
> 
> 1. Device enumeration
>   After booting into Linux, the new device appears on I3C bus 5:
> 
> root@ast2600-default:/sys/bus/i3c/devices# ls
> 0-4cc31020000  0-4cc51180000  0-4cc51181000  1-4cc31020000
> 1-4cc51180000  1-4cc51181000  4-target       5-0            i3c-0
> i3c-1          i3c-2          i3c-3          i3c-4          i3c-5
> 
> 1. READ/WRITE MOCK EEPROM
> I verified private write and read operations using the i3cdev interface
> 
> root@ast2600-default:/sys/bus/i3c/devices/5-0# dd if=/tmp/jamin
> of=/dev/i3c-5-0
> 0+1 records in
> 0+1 records out
> 200 bytes (200B) copied, 0.002032 seconds, 96.1KB/s
> 
> root@ast2600-default:/sys/bus/i3c/devices/5-0# hexdump /dev/i3c-5-0
> 0000000 04cb 2d84 0d80 45e6 6c9a 3d23 9384 b3ef
> 0000010 f534 3328 5e07 ac94 5cd6 3914 86ad e085
> 0000020 e047 81e3 af52 bb88 f20c c282 6148 5374
> 0000030 6b7d 58bf fb1c 2382 121f 1a60 bfb4 1ebd
> 0000040 8028 0a82 4740 8287 5737 988f 597e 9a67
> 0000050 a7f7 b0c8 db87 2631 8304 df89 6977 2a82
> 0000060 12d8 fb73 bcc7 ecd0 eba2 575f a050 02fb
> 0000070 af4b ffef da5b 5cb3 14a3 7047 17ac d238
> 0000080 eda6 ae3e ac72 6112 bbbf fbca 844d 035e
> 0000090 0970 f591 7536 8312 0552 d4fd 817b b323
> 00000a0 398b e633 df77 59ee fd4e 6922 e4a9 a160
> 00000b0 d206 96e1 a915 782b 1b53 a9bc 70c6 5670
> 00000c0 6dfe a3de ca1f bd0a
> 00000c8
> 
> root@ast2600-default:/sys/bus/i3c/devices/5-0# hexdump /tmp/jamin
> 0000000 04cb 2d84 0d80 45e6 6c9a 3d23 9384 b3ef
> 0000010 f534 3328 5e07 ac94 5cd6 3914 86ad e085
> 0000020 e047 81e3 af52 bb88 f20c c282 6148 5374
> 0000030 6b7d 58bf fb1c 2382 121f 1a60 bfb4 1ebd
> 0000040 8028 0a82 4740 8287 5737 988f 597e 9a67
> 0000050 a7f7 b0c8 db87 2631 8304 df89 6977 2a82
> 0000060 12d8 fb73 bcc7 ecd0 eba2 575f a050 02fb
> 0000070 af4b ffef da5b 5cb3 14a3 7047 17ac d238
> 0000080 eda6 ae3e ac72 6112 bbbf fbca 844d 035e
> 0000090 0970 f591 7536 8312 0552 d4fd 817b b323
> 00000a0 398b e633 df77 59ee fd4e 6922 e4a9 a160
> 00000b0 d206 96e1 a915 782b 1b53 a9bc 70c6 5670
> 00000c0 6dfe a3de ca1f bd0a
> 00000c8
> 
> root@ast2600-default:/sys/bus/i3c/devices/5-0# dd if=/dev/i3c-5-0 bs=1
> count=200 2>/dev/null | cmp - /tmp/jamin && echo "PASS" || echo "FAIL"
> PASS
> 
> The data read back from /dev/i3c-5-0 matches the original file exactly, and the
> comparison reports PASS.
> This confirms that the mock I3C target works correctly as an EEPROM-like
> device and that the TX/RX data path through the DW I3C controller model
> functions as expected on AST2600.
> 
> Thanks,
> Jamin

This patch series,

Tested-by: Jamin Lin <jamin_lin@aspeedtech.com>

Thanks,
Jamin