Allows for easier looping over entries when adding CHMU and CPMU instances.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
CHMU RFC v2: New patch to simplify a few code paths.
---
include/hw/cxl/cxl_pci.h | 17 ++++++++++-------
hw/cxl/switch-mailbox-cci.c | 4 ++--
hw/mem/cxl_type3.c | 12 ++++++++----
hw/pci-bridge/cxl_downstream.c | 4 ++--
hw/pci-bridge/cxl_root_port.c | 4 ++--
hw/pci-bridge/cxl_upstream.c | 4 ++--
6 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h
index d0855ed78b..00a0335d55 100644
--- a/include/hw/cxl/cxl_pci.h
+++ b/include/hw/cxl/cxl_pci.h
@@ -161,6 +161,12 @@ typedef struct CXLDVSECPortFlexBus {
} CXLDVSECPortFlexBus;
QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x20);
+/* Only applies to the type 3 device emulation */
+enum register_locator_indicies {
+ REG_LOC_IDX_COMPONENT,
+ REG_LOC_IDX_DEVICE,
+ NR_REG_LOC_IDX
+};
/*
* CXL r3.1 Section 8.1.9: Register Locator DVSEC
* DVSEC ID: 8, Revision 0
@@ -168,14 +174,11 @@ QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x20);
typedef struct CXLDVSECRegisterLocator {
DVSECHeader hdr;
uint16_t rsvd;
- uint32_t reg0_base_lo;
- uint32_t reg0_base_hi;
- uint32_t reg1_base_lo;
- uint32_t reg1_base_hi;
- uint32_t reg2_base_lo;
- uint32_t reg2_base_hi;
+ struct {
+ uint32_t lo;
+ uint32_t hi;
+ } reg_base[NR_REG_LOC_IDX];
} CXLDVSECRegisterLocator;
-QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24);
/* BAR Equivalence Indicator */
#define BEI_BAR_10H 0
diff --git a/hw/cxl/switch-mailbox-cci.c b/hw/cxl/switch-mailbox-cci.c
index 223f220433..af91525445 100644
--- a/hw/cxl/switch-mailbox-cci.c
+++ b/hw/cxl/switch-mailbox-cci.c
@@ -50,8 +50,8 @@ static void cswbcci_realize(PCIDevice *pci_dev, Error **errp)
&cxl_dstate->device_registers);
regloc_dvsec = &(CXLDVSECRegisterLocator) {
.rsvd = 0,
- .reg0_base_lo = RBI_CXL_DEVICE_REG | 0,
- .reg0_base_hi = 0,
+ .reg_base[0].lo = RBI_CXL_DEVICE_REG | 0,
+ .reg_base[0].hi = 0,
};
cxl_component_create_dvsec(cxl_cstate, CXL3_SWITCH_MAILBOX_CCI,
REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index ca9fe89e4f..dcefd41088 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -386,10 +386,14 @@ static void build_dvsecs(CXLType3Dev *ct3d)
dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
.rsvd = 0,
- .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
- .reg0_base_hi = 0,
- .reg1_base_lo = RBI_CXL_DEVICE_REG | CXL_DEVICE_REG_BAR_IDX,
- .reg1_base_hi = 0,
+ .reg_base[REG_LOC_IDX_COMPONENT] = {
+ .lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
+ .hi = 0,
+ },
+ .reg_base[REG_LOC_IDX_DEVICE] = {
+ .lo = RBI_CXL_DEVICE_REG | CXL_DEVICE_REG_BAR_IDX,
+ .hi = 0,
+ },
};
cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE,
REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
index 1065245a8b..387cebbb98 100644
--- a/hw/pci-bridge/cxl_downstream.c
+++ b/hw/pci-bridge/cxl_downstream.c
@@ -126,8 +126,8 @@ static void build_dvsecs(CXLComponentState *cxl)
dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
.rsvd = 0,
- .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
- .reg0_base_hi = 0,
+ .reg_base[0].lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
+ .reg_base[0].hi = 0,
};
cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index e6a4035d26..d955f3bcc5 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -136,8 +136,8 @@ static void build_dvsecs(CXLComponentState *cxl)
dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
.rsvd = 0,
- .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
- .reg0_base_hi = 0,
+ .reg_base[0].lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
+ .reg_base[0].hi = 0,
};
cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
index 208e0c6172..28f7542814 100644
--- a/hw/pci-bridge/cxl_upstream.c
+++ b/hw/pci-bridge/cxl_upstream.c
@@ -129,8 +129,8 @@ static void build_dvsecs(CXLComponentState *cxl)
dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
.rsvd = 0,
- .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
- .reg0_base_hi = 0,
+ .reg_base[0].lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
+ .reg_base[0].hi = 0,
};
cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
--
2.48.1