Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
target/riscv/cpu.c | 3 ++
target/riscv/cpu_cfg.h | 5 +++
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans/trans_xmips.c.inc | 39 +++++++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 3 ++
target/riscv/xmips.decode | 11 +++++++
7 files changed, 63 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
create mode 100644 target/riscv/xmips.decode
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db2ad1c08d..f5234a620a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -242,6 +242,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
{ },
};
@@ -1360,6 +1361,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
+ MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
{ },
};
@@ -3180,6 +3182,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.pmp = true,
.cfg.ext_zba = true,
.cfg.ext_zbb = true,
+ .cfg.ext_xmipscmov = true,
.cfg.marchid = 0x8000000000000201,
#ifndef CONFIG_USER_ONLY
.custom_csrs = mips_csr_list,
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index aa28dc8d7e..2db471ad17 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
return true;
}
+static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
+{
+ return cfg->ext_xmipscmov;
+}
+
static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
{
return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index 59f134a419..baedf0c466 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -145,6 +145,7 @@ BOOL_FIELD(ext_xtheadmemidx)
BOOL_FIELD(ext_xtheadmempair)
BOOL_FIELD(ext_xtheadsync)
BOOL_FIELD(ext_XVentanaCondOps)
+BOOL_FIELD(ext_xmipscmov)
BOOL_FIELD(mmu)
BOOL_FIELD(pmp)
diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
new file mode 100644
index 0000000000..5437148af1
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xmips.c.inc
@@ -0,0 +1,39 @@
+/*
+ * RISC-V translation routines for the MIPS extensions (xmips*).
+ *
+ * Copyright (c) 2025 MIPS
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2.1 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_XMIPSCMOV(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xmipscmov) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
+{
+ REQUIRE_XMIPSCMOV(ctx);
+
+ TCGv zero, source1, source2, source3;
+ zero = tcg_constant_tl(0);
+ source1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ source2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ source3 = get_gpr(ctx, a->rs3, EXT_NONE);
+
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd],
+ source2, zero, source1, source3);
+
+ return true;
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index fbb6c8fb45..26cd11ec00 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -4,6 +4,7 @@ gen = [
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
+ decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),
]
riscv_ss = ss.source_set()
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2cba1a26a7..a550599e6d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1194,8 +1194,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_rvbf16.c.inc"
#include "decode-xthead.c.inc"
+#include "decode-xmips.c.inc"
#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
+#include "insn_trans/trans_xmips.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
@@ -1211,6 +1213,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
const RISCVDecoder decoder_table[] = {
{ always_true_p, decode_insn32 },
+ { has_xmips_p, decode_xmips},
{ has_xthead_p, decode_xthead},
{ has_XVentanaCondOps_p, decode_XVentanaCodeOps},
};
diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
new file mode 100644
index 0000000000..cb334fa4bd
--- /dev/null
+++ b/target/riscv/xmips.decode
@@ -0,0 +1,11 @@
+#
+# RISC-V translation routines for the MIPS extension
+#
+# Copyright (c) 2025 MIPS
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: MIPS P8700 instructions
+# (https://mips.com/products/hardware/p8700/)
+
+ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
--
2.34.1On Mon, Jun 2, 2025 at 11:13 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Add mips.ccmov defined by Xmipscmov.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
> target/riscv/cpu.c | 3 ++
> target/riscv/cpu_cfg.h | 5 +++
> target/riscv/cpu_cfg_fields.h.inc | 1 +
> target/riscv/insn_trans/trans_xmips.c.inc | 39 +++++++++++++++++++++++
> target/riscv/meson.build | 1 +
> target/riscv/translate.c | 3 ++
> target/riscv/xmips.decode | 11 +++++++
> 7 files changed, 63 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
> create mode 100644 target/riscv/xmips.decode
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2ad1c08d..f5234a620a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -242,6 +242,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
> ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
> + ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
>
> { },
> };
> @@ -1360,6 +1361,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
> MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
> MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
> MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
> + MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
>
> { },
> };
> @@ -3180,6 +3182,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.pmp = true,
> .cfg.ext_zba = true,
> .cfg.ext_zbb = true,
> + .cfg.ext_xmipscmov = true,
> .cfg.marchid = 0x8000000000000201,
> #ifndef CONFIG_USER_ONLY
> .custom_csrs = mips_csr_list,
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index aa28dc8d7e..2db471ad17 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
> return true;
> }
>
> +static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
> +{
> + return cfg->ext_xmipscmov;
> +}
> +
> static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
> {
> return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
> index 59f134a419..baedf0c466 100644
> --- a/target/riscv/cpu_cfg_fields.h.inc
> +++ b/target/riscv/cpu_cfg_fields.h.inc
> @@ -145,6 +145,7 @@ BOOL_FIELD(ext_xtheadmemidx)
> BOOL_FIELD(ext_xtheadmempair)
> BOOL_FIELD(ext_xtheadsync)
> BOOL_FIELD(ext_XVentanaCondOps)
> +BOOL_FIELD(ext_xmipscmov)
>
> BOOL_FIELD(mmu)
> BOOL_FIELD(pmp)
> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
> new file mode 100644
> index 0000000000..5437148af1
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
> @@ -0,0 +1,39 @@
> +/*
> + * RISC-V translation routines for the MIPS extensions (xmips*).
Can you include links to documentation here
Alistair
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2.1 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_XMIPSCMOV(ctx) do { \
> + if (!ctx->cfg_ptr->ext_xmipscmov) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
> +{
> + REQUIRE_XMIPSCMOV(ctx);
> +
> + TCGv zero, source1, source2, source3;
> + zero = tcg_constant_tl(0);
> + source1 = get_gpr(ctx, a->rs1, EXT_NONE);
> + source2 = get_gpr(ctx, a->rs2, EXT_NONE);
> + source3 = get_gpr(ctx, a->rs3, EXT_NONE);
> +
> + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd],
> + source2, zero, source1, source3);
> +
> + return true;
> +}
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index fbb6c8fb45..26cd11ec00 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -4,6 +4,7 @@ gen = [
> decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
> decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
> decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
> + decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),
> ]
>
> riscv_ss = ss.source_set()
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2cba1a26a7..a550599e6d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1194,8 +1194,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_svinval.c.inc"
> #include "insn_trans/trans_rvbf16.c.inc"
> #include "decode-xthead.c.inc"
> +#include "decode-xmips.c.inc"
> #include "insn_trans/trans_xthead.c.inc"
> #include "insn_trans/trans_xventanacondops.c.inc"
> +#include "insn_trans/trans_xmips.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> #include "decode-insn16.c.inc"
> @@ -1211,6 +1213,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>
> const RISCVDecoder decoder_table[] = {
> { always_true_p, decode_insn32 },
> + { has_xmips_p, decode_xmips},
> { has_xthead_p, decode_xthead},
> { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
> };
> diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
> new file mode 100644
> index 0000000000..cb334fa4bd
> --- /dev/null
> +++ b/target/riscv/xmips.decode
> @@ -0,0 +1,11 @@
> +#
> +# RISC-V translation routines for the MIPS extension
> +#
> +# Copyright (c) 2025 MIPS
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference: MIPS P8700 instructions
> +# (https://mips.com/products/hardware/p8700/)
> +
> +ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
> --
> 2.34.1
>
On 10. 6. 25. 13:39, Alistair Francis wrote:
> [You don't often get email from alistair23@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Mon, Jun 2, 2025 at 11:13 PM Djordje Todorovic
> <Djordje.Todorovic@htecgroup.com> wrote:
>> Add mips.ccmov defined by Xmipscmov.
>>
>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> ---
>> target/riscv/cpu.c | 3 ++
>> target/riscv/cpu_cfg.h | 5 +++
>> target/riscv/cpu_cfg_fields.h.inc | 1 +
>> target/riscv/insn_trans/trans_xmips.c.inc | 39 +++++++++++++++++++++++
>> target/riscv/meson.build | 1 +
>> target/riscv/translate.c | 3 ++
>> target/riscv/xmips.decode | 11 +++++++
>> 7 files changed, 63 insertions(+)
>> create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>> create mode 100644 target/riscv/xmips.decode
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index db2ad1c08d..f5234a620a 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -242,6 +242,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>> ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
>> ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
>> ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
>> + ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov),
>>
>> { },
>> };
>> @@ -1360,6 +1361,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>> MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
>> MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
>> MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
>> + MULTI_EXT_CFG_BOOL("xmipscmov", ext_xmipscmov, false),
>>
>> { },
>> };
>> @@ -3180,6 +3182,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>> .cfg.pmp = true,
>> .cfg.ext_zba = true,
>> .cfg.ext_zbb = true,
>> + .cfg.ext_xmipscmov = true,
>> .cfg.marchid = 0x8000000000000201,
>> #ifndef CONFIG_USER_ONLY
>> .custom_csrs = mips_csr_list,
>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>> index aa28dc8d7e..2db471ad17 100644
>> --- a/target/riscv/cpu_cfg.h
>> +++ b/target/riscv/cpu_cfg.h
>> @@ -36,6 +36,11 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg __attribute__((__unus
>> return true;
>> }
>>
>> +static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
>> +{
>> + return cfg->ext_xmipscmov;
>> +}
>> +
>> static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
>> {
>> return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
>> diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
>> index 59f134a419..baedf0c466 100644
>> --- a/target/riscv/cpu_cfg_fields.h.inc
>> +++ b/target/riscv/cpu_cfg_fields.h.inc
>> @@ -145,6 +145,7 @@ BOOL_FIELD(ext_xtheadmemidx)
>> BOOL_FIELD(ext_xtheadmempair)
>> BOOL_FIELD(ext_xtheadsync)
>> BOOL_FIELD(ext_XVentanaCondOps)
>> +BOOL_FIELD(ext_xmipscmov)
>>
>> BOOL_FIELD(mmu)
>> BOOL_FIELD(pmp)
>> diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc
>> new file mode 100644
>> index 0000000000..5437148af1
>> --- /dev/null
>> +++ b/target/riscv/insn_trans/trans_xmips.c.inc
>> @@ -0,0 +1,39 @@
>> +/*
>> + * RISC-V translation routines for the MIPS extensions (xmips*).
> Can you include links to documentation here
>
> Alistair
>
Sure. I will include it in v3.
Thanks!
Djordje
>> + *
>> + * Copyright (c) 2025 MIPS
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2.1 or later, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#define REQUIRE_XMIPSCMOV(ctx) do { \
>> + if (!ctx->cfg_ptr->ext_xmipscmov) { \
>> + return false; \
>> + } \
>> +} while (0)
>> +
>> +static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)
>> +{
>> + REQUIRE_XMIPSCMOV(ctx);
>> +
>> + TCGv zero, source1, source2, source3;
>> + zero = tcg_constant_tl(0);
>> + source1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + source2 = get_gpr(ctx, a->rs2, EXT_NONE);
>> + source3 = get_gpr(ctx, a->rs3, EXT_NONE);
>> +
>> + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[a->rd],
>> + source2, zero, source1, source3);
>> +
>> + return true;
>> +}
>> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
>> index fbb6c8fb45..26cd11ec00 100644
>> --- a/target/riscv/meson.build
>> +++ b/target/riscv/meson.build
>> @@ -4,6 +4,7 @@ gen = [
>> decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
>> decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
>> decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
>> + decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),
>> ]
>>
>> riscv_ss = ss.source_set()
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 2cba1a26a7..a550599e6d 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -1194,8 +1194,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>> #include "insn_trans/trans_svinval.c.inc"
>> #include "insn_trans/trans_rvbf16.c.inc"
>> #include "decode-xthead.c.inc"
>> +#include "decode-xmips.c.inc"
>> #include "insn_trans/trans_xthead.c.inc"
>> #include "insn_trans/trans_xventanacondops.c.inc"
>> +#include "insn_trans/trans_xmips.c.inc"
>>
>> /* Include the auto-generated decoder for 16 bit insn */
>> #include "decode-insn16.c.inc"
>> @@ -1211,6 +1213,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>>
>> const RISCVDecoder decoder_table[] = {
>> { always_true_p, decode_insn32 },
>> + { has_xmips_p, decode_xmips},
>> { has_xthead_p, decode_xthead},
>> { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
>> };
>> diff --git a/target/riscv/xmips.decode b/target/riscv/xmips.decode
>> new file mode 100644
>> index 0000000000..cb334fa4bd
>> --- /dev/null
>> +++ b/target/riscv/xmips.decode
>> @@ -0,0 +1,11 @@
>> +#
>> +# RISC-V translation routines for the MIPS extension
>> +#
>> +# Copyright (c) 2025 MIPS
>> +#
>> +# SPDX-License-Identifier: LGPL-2.1-or-later
>> +#
>> +# Reference: MIPS P8700 instructions
>> +# (https://mips.com/products/hardware/p8700/)
>> +
>> +ccmov rs3:5 11 rs2:5 rs1:5 011 rd:5 0001011
>> --
>> 2.34.1
>>
© 2016 - 2025 Red Hat, Inc.