[v2] riscv: Add support for MIPS P8700 CPU

[PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

Posted by Djordje Todorovic 5 months, 2 weeks ago

Add a new function, so we can change reset vector from platforms.

Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu.h       | 2 ++
 target/riscv/translate.c | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 229ade9ed9..c0e048a66d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -656,6 +656,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
+void cpu_set_exception_base(int vp_index, target_ulong address);
+
 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 FIELD(TB_FLAGS, FS, 3, 2)
 /* Vector flags */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d7a6de02df..2cba1a26a7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1427,3 +1427,11 @@ void riscv_translate_init(void)
     load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
                              "load_val");
 }
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+#ifndef CONFIG_USER_ONLY
+    RISCVCPU *vp = RISCV_CPU(qemu_get_cpu(vp_index));
+    vp->env.resetvec = address;
+#endif
+}
-- 
2.34.1

Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

Posted by Alistair Francis 5 months, 1 week ago

On Mon, Jun 2, 2025 at 11:15 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Add a new function, so we can change reset vector from platforms.

You can use the "resetvec" property instead, there are a range of
RISC-V machines already doing this. Have a look at
hw/riscv/opentitan.c or hw/riscv/sifive_u.c for examples

Alistair

>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
>  target/riscv/cpu.h       | 2 ++
>  target/riscv/translate.c | 8 ++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 229ade9ed9..c0e048a66d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -656,6 +656,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
>  target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> +void cpu_set_exception_base(int vp_index, target_ulong address);
> +
>  FIELD(TB_FLAGS, MEM_IDX, 0, 3)
>  FIELD(TB_FLAGS, FS, 3, 2)
>  /* Vector flags */
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d7a6de02df..2cba1a26a7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1427,3 +1427,11 @@ void riscv_translate_init(void)
>      load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
>                               "load_val");
>  }
> +
> +void cpu_set_exception_base(int vp_index, target_ulong address)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    RISCVCPU *vp = RISCV_CPU(qemu_get_cpu(vp_index));
> +    vp->env.resetvec = address;
> +#endif
> +}
> --
> 2.34.1
>

Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

Posted by Philippe Mathieu-Daudé 5 months, 1 week ago

On 2/6/25 15:12, Djordje Todorovic wrote:
> Add a new function, so we can change reset vector from platforms.
> 
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
>   target/riscv/cpu.h       | 2 ++
>   target/riscv/translate.c | 8 ++++++++
>   2 files changed, 10 insertions(+)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 229ade9ed9..c0e048a66d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -656,6 +656,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
>   target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>   void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>   
 > +void cpu_set_exception_base(int vp_index, target_ulong address);

If we need that, that'd be declared as:

#ifndef CONFIG_USER_ONLY
void riscv_cpu_set_exception_base(int vp_index, target_ulong address);
#endif

Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

Posted by Djordje Todorovic 5 months ago

On 10. 6. 25. 09:43, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do 
> not click links or open attachments unless you recognize the sender 
> and know the content is safe.
>
>
> On 2/6/25 15:12, Djordje Todorovic wrote:
>> Add a new function, so we can change reset vector from platforms.
>>
>> Signed-off-by: Chao-ying Fu <cfu@mips.com>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> ---
>>   target/riscv/cpu.h       | 2 ++
>>   target/riscv/translate.c | 8 ++++++++
>>   2 files changed, 10 insertions(+)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 229ade9ed9..c0e048a66d 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -656,6 +656,8 @@ G_NORETURN void 
>> riscv_raise_exception(CPURISCVState *env,
>>   target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>>   void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>
> > +void cpu_set_exception_base(int vp_index, target_ulong address);
>
> If we need that, that'd be declared as:
>
> #ifndef CONFIG_USER_ONLY
> void riscv_cpu_set_exception_base(int vp_index, target_ulong address);
> #endif
>
We want to be able to change "resetvec" during runtime, so we do need

this. Sure, I will do it that way in v3.

Thanks!